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1. 发明授权

US06870379B1 Indirect stimulation of an integrated circuit die 失效
标题翻译：间接刺激集成电路管芯
公开(公告)号：US06870379B1
公开(公告)日：2005-03-22
申请号：US10164739
申请日：2002-06-06
申请人： Brennan V. Davis , Victoria J. Bruce , Michael R. Bruce , Rosalinda M. Ring , David H. Eppes
发明人： Brennan V. Davis , Victoria J. Bruce , Michael R. Bruce , Rosalinda M. Ring , David H. Eppes
IPC分类号： G01R31/311 , G01R31/302 , G01R31/26
CPC分类号： G01R31/311
摘要： Analysis of a semiconductor die is enhanced by the stimulation the die and the detection of a response to the stimulation. According to an example embodiment of the present invention, a semiconductor die is analyzed using indirect stimulation of a portion of the die, and detecting a response therefrom. First, selected portion of circuitry within the die is stimulated. The stimulation of the selected portion induces a second portion of circuitry within the die to generate an external emission. The emission is detected and the die is analyzed therefrom. In one particular implementation, a response from the selected portion is inhibited from interfering with the detection of the emission from the second portion of circuitry.
摘要翻译：通过刺激模具和检测对刺激的响应来增强半导体管芯的分析。根据本发明的示例性实施例，使用间接刺激芯片的一部分并且从其检测响应来分析半导体管芯。首先，刺激模具内的电路的选定部分。所选部分的刺激引起管芯内的电路的第二部分以产生外部发射。检测发射并从中分析模具。在一个具体实现中，来自所选择的部分的响应被禁止干扰来自电路的第二部分的发射的检测。

2. 发明授权

US06483327B1 Quadrant avalanche photodiode time-resolved detection 失效
标题翻译：象限雪崩光电二极管时间分辨检测
公开(公告)号：US06483327B1
公开(公告)日：2002-11-19
申请号：US09409088
申请日：1999-09-30
申请人： Michael R. Bruce , Victoria J. Bruce , Jeffrey D. Birdsley , Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis
发明人： Michael R. Bruce , Victoria J. Bruce , Jeffrey D. Birdsley , Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis
IPC分类号： G01R31302
CPC分类号： G01R1/071 , G01R31/311
摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.
摘要翻译：一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。光圈元件被定位成用于观看集成电路的选定区域。位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

3. 发明授权

US06635839B1 Semiconductor analysis arrangement and method therefor 有权
标题翻译：半导体分析安排及其方法
公开(公告)号：US06635839B1
公开(公告)日：2003-10-21
申请号：US09838672
申请日：2001-04-19
申请人： Glen P. Gilfeather , Srikar V. Chunduri , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
发明人： Glen P. Gilfeather , Srikar V. Chunduri , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
IPC分类号： B07C500
CPC分类号： G01N21/9501 , G01R31/311
摘要： Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.
摘要翻译：使用适于扰动测试室中的管芯并检测从管芯到扰动的响应的系统来增强半导体管芯分析。根据本发明的示例性实施例，半导体管芯分析系统包括测试室和适于与测试室对接的对接装置。模具保持在对接装置中，并且当对接装置与腔室对接时，将模具放置在测试室的内部。使用两个或更多个扰动装置扰乱管芯，并且控制器适于控制扰动。数据采集装置响应于扰动从管芯接收数据，并且数据用于分析管芯。

4. 发明授权

US06844928B1 Fiber optic semiconductor analysis arrangement and method therefor 失效
标题翻译：光纤半导体分析布置及其方法
公开(公告)号：US06844928B1
公开(公告)日：2005-01-18
申请号：US09838717
申请日：2001-04-19
申请人： Glen P. Gilfeather , Srikar V. Chunduri , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
发明人： Glen P. Gilfeather , Srikar V. Chunduri , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
IPC分类号： G01N21/95 , G01N21/00
CPC分类号： G01N21/9501
摘要： The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.
摘要翻译：使用在光源和管芯之间引导光的方法和装置来增强基于光的半导体管芯分析的可操作性。在本发明的一个示例实施例中，使用光纤电缆将光源引导到半导体分析装置中的管芯。分析装置适于使用经由光纤电缆接收的光来分析模具。该分析包括一种或多种基于光的应用，例如用光刺激所述裸片的选定部分并检测其中的响应。以这种方式，可以在各种分析实现中将光导向模具，例如用于在测试室中分析模具。

5. 发明授权

US06700659B1 Semiconductor analysis arrangement and method therefor 失效
标题翻译：半导体分析安排及其方法
公开(公告)号：US06700659B1
公开(公告)日：2004-03-02
申请号：US09838671
申请日：2001-04-19
申请人： Srikar V. Chunduri , Glen P. Gilfeather , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
发明人： Srikar V. Chunduri , Glen P. Gilfeather , Brennan V. Davis , David H. Eppes , Victoria Bruce , Michael Bruce , Rosalinda M. Ring , Daniel Stone
IPC分类号： G01N2188
CPC分类号： G01R31/311 , G01N21/9501
摘要： The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.
摘要翻译：使用可以检测光源和管芯之间的光泄漏的方法和装置来增强基于光的半导体管芯分析的可操作性。在本发明的一个示例性实施例中，使用例如光纤电缆将光源引导到半导体分析装置。分析装置适于使用来自光源的光来分析模具。光检测装置检测来自系统的光泄漏的状况，并产生表示漏光状况的信号。所产生的信号然后可以用于控制半导体分析装置，例如通过响应于检测到的泄漏而停用光源，或者通过允许光源响应于不检测泄漏而起作用。

6. 发明授权

US06421811B1 Defect detection via acoustic analysis 失效
标题翻译：通过声学分析进行缺陷检测
公开(公告)号：US06421811B1
公开(公告)日：2002-07-16
申请号：US09409498
申请日：1999-09-30
申请人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
发明人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： G06F1750
CPC分类号： G01R31/2898 , G01N29/2418 , G01N2291/012 , G01N2291/2698 , G01R31/2851 , G01R31/311
摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of acoustic energy. Acoustic energy propagating through the device is detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed from the detected energy and correlated to a particular defect in the device.
摘要翻译：根据本发明的示例性实施例，缺陷检测方法包括检测作为声能的函数的集成电路中的缺陷的存在。检测通过装置传播的声能。从检测到的能量开发包括振幅，频率，相位或频谱等信息的参数，并将其与设备中的特定缺陷相关联。

7. 发明授权

US06350624B1 Substrate removal as a functional of sonic analysis 失效
标题翻译：基底去除作为声波分析的函数
公开(公告)号：US06350624B1
公开(公告)日：2002-02-26
申请号：US09409304
申请日：1999-09-29
申请人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
发明人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： H01L21302
CPC分类号： G01N1/32 , G01R31/311
摘要： Substrate removal for post-manufacturing analysis of a semiconductor device is enhanced via a method and system that use sonic energy in the control of the removal process. According to an example embodiment of the present invention, sonic energy is reflected off of a region of a semiconductor chip having a portion of substrate removed from the back side of the chip. The reflections are detected and used to determine the thickness of substrate in the back side. In this manner, the substrate removal process can be efficiently and accurately controlled.
摘要翻译：通过在控制去除过程中使用声能的方法和系统来增强用于半导体器件后制造分析的衬底去除。根据本发明的示例性实施例，声能被从芯片的背面去除的衬底的一部分的半导体芯片的区域反射出来。检测反射并用于确定背面底物的厚度。以这种方式，可以有效且准确地控制基板去除处理。

8. 发明授权

US06303396B1 Substrate removal as a function of resistance at the back side of a semiconductor device 有权
标题翻译：作为半导体器件背面的电阻的函数的衬底去除
公开(公告)号：US06303396B1
公开(公告)日：2001-10-16
申请号：US09408881
申请日：1999-09-29
申请人： Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis , Jeffrey D. Birdsley , Michael R. Bruce
发明人： Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis , Jeffrey D. Birdsley , Michael R. Bruce
IPC分类号： H01L2166
CPC分类号： G01R31/2898 , H01L22/10 , H01L22/14 , H01L2924/014
摘要： A resistance monitoring approach is used for removing substrate from a back side of a semiconductor device. According to an example embodiment of the present invention, substrate is removed from a semiconductor device having a circuit side opposite the back side and a resistance path in silicon substrate. The change in resistance of the resistance path is monitored. The change in resistance provides an indication of the progress of the substrate removal process. Using the change in resistance, the substrate removal process is controlled.
摘要翻译：电阻监测方法用于从半导体器件的背面去除衬底。根据本发明的示例性实施例，从具有与背面相反的电路侧和硅衬底中的电阻路径的半导体器件中去除衬底。监测电阻路径的电阻变化。电阻的变化提供了衬底移除过程进展的指示。使用电阻的变化，控制衬底去除过程。

9. 发明授权

US06448096B1 Atomic force microscopy and signal acquisition via buried insulator 失效
标题翻译：原子力显微镜和通过埋层绝缘子的信号采集
公开(公告)号：US06448096B1
公开(公告)日：2002-09-10
申请号：US09864656
申请日：2001-05-23
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2100
CPC分类号： G01Q60/30 , G01R31/303 , Y10S977/854
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching the insulator layer of the SOI structure. According to an example embodiment of the present invention, a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side is analyzed. An atomic force microscope is scanned across a thinned portion of the back side. The microscope responds to an electrical characteristic, such as a logic state, coupled from circuitry via the insulator portion of the die over which the microscope is being scanned. The response of the microscope to the die is detected and used to detect an electrical characteristic of the die.
摘要翻译：通过从背面访问管芯内的电路而不必破坏SOI结构的绝缘体层来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。根据本发明的示例性实施例，分析了具有SOI结构的半导体管芯和电路侧的背面相反的电路。原子力显微镜扫描在背面的薄部分。显微镜响应诸如逻辑状态的电特性，该电特性通过显微镜正被扫描的裸片的绝缘体部分从电路耦合。检测显微镜对管芯的响应，并用于检测管芯的电气特性。

10. 发明授权

US06448095B1 Circuit access and analysis for a SOI flip-chip die 失效
标题翻译： SOI倒装芯片的电路访问和分析
公开(公告)号：US06448095B1
公开(公告)日：2002-09-10
申请号：US09755013
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2100
CPC分类号： H01L22/20 , G01R31/307
摘要： Analysis of a flip-chip type IC die having SOI structure is enhanced via analysis and repair of the die that make possible analysis that would typically result in the die being in a state of disrepair. According to an example embodiment of the present invention, a focused ion beam (FIB) is directed at a back side of a flip-chip die having a circuitry in a circuit side opposite a back side, wherein the circuitry including silicon on insulator (SOI) structure. The FIB is used to remove a selected portion of substrate including a portion of the insulator of the SOI structure from the die. The removed substrate exposes an insulator region in the die, and a signal is coupled from circuitry in the die via the exposed insulator region and used to analyze the die. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed. The reconstruction takes place before, during or after the signal is coupled, depending upon the die being analyzed and the type of analysis being performed. In this manner, access for analyzing the die is improved via the ability to couple a signal through the insulator and to repair a portion of the die that has been altered for analysis. Analysis that would otherwise be destructive can be performed and the ability of the die to function after analysis can be maintained.
摘要翻译：具有SOI结构的倒装芯片型IC芯片的分析通过分析和修复模具得到增强，这使得可能的分析通常导致模具处于失修状态。根据本发明的一个示例性实施例，聚焦离子束（FIB）指向倒装芯片的背面，该倒装芯片的背面具有电路侧的电路，其中包括绝缘体上的硅（SOI））结构体。 FIB用于从芯片去除包括SOI结构的绝缘体的一部分的衬底的选定部分。去除的衬底暴露了管芯中的绝缘体区域，并且信号通过暴露的绝缘体区域从管芯中的电路耦合并用于分析管芯。材料沉积在暴露的区域中，并且已经去除的模具的选定部分被重建。重建在信号耦合之前，期间或之后进行，这取决于正在分析的管芯和正在执行的分析的类型。以这种方式，通过能够通过绝缘体耦合信号并修复已经被改变以用于分析的芯片的一部分的能力来提高用于分析芯片的访问。否则可以进行破坏性的分析，可以保持分析后的模具功能的能力。

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