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1. 发明授权

US06448096B1 Atomic force microscopy and signal acquisition via buried insulator 失效
标题翻译：原子力显微镜和通过埋层绝缘子的信号采集
公开(公告)号：US06448096B1
公开(公告)日：2002-09-10
申请号：US09864656
申请日：2001-05-23
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2100
CPC分类号： G01Q60/30 , G01R31/303 , Y10S977/854
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching the insulator layer of the SOI structure. According to an example embodiment of the present invention, a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side is analyzed. An atomic force microscope is scanned across a thinned portion of the back side. The microscope responds to an electrical characteristic, such as a logic state, coupled from circuitry via the insulator portion of the die over which the microscope is being scanned. The response of the microscope to the die is detected and used to detect an electrical characteristic of the die.
摘要翻译：通过从背面访问管芯内的电路而不必破坏SOI结构的绝缘体层来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。根据本发明的示例性实施例，分析了具有SOI结构的半导体管芯和电路侧的背面相反的电路。原子力显微镜扫描在背面的薄部分。显微镜响应诸如逻辑状态的电特性，该电特性通过显微镜正被扫描的裸片的绝缘体部分从电路耦合。检测显微镜对管芯的响应，并用于检测管芯的电气特性。

2. 发明授权

US06448095B1 Circuit access and analysis for a SOI flip-chip die 失效
标题翻译： SOI倒装芯片的电路访问和分析
公开(公告)号：US06448095B1
公开(公告)日：2002-09-10
申请号：US09755013
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2100
CPC分类号： H01L22/20 , G01R31/307
摘要： Analysis of a flip-chip type IC die having SOI structure is enhanced via analysis and repair of the die that make possible analysis that would typically result in the die being in a state of disrepair. According to an example embodiment of the present invention, a focused ion beam (FIB) is directed at a back side of a flip-chip die having a circuitry in a circuit side opposite a back side, wherein the circuitry including silicon on insulator (SOI) structure. The FIB is used to remove a selected portion of substrate including a portion of the insulator of the SOI structure from the die. The removed substrate exposes an insulator region in the die, and a signal is coupled from circuitry in the die via the exposed insulator region and used to analyze the die. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed. The reconstruction takes place before, during or after the signal is coupled, depending upon the die being analyzed and the type of analysis being performed. In this manner, access for analyzing the die is improved via the ability to couple a signal through the insulator and to repair a portion of the die that has been altered for analysis. Analysis that would otherwise be destructive can be performed and the ability of the die to function after analysis can be maintained.
摘要翻译：具有SOI结构的倒装芯片型IC芯片的分析通过分析和修复模具得到增强，这使得可能的分析通常导致模具处于失修状态。根据本发明的一个示例性实施例，聚焦离子束（FIB）指向倒装芯片的背面，该倒装芯片的背面具有电路侧的电路，其中包括绝缘体上的硅（SOI））结构体。 FIB用于从芯片去除包括SOI结构的绝缘体的一部分的衬底的选定部分。去除的衬底暴露了管芯中的绝缘体区域，并且信号通过暴露的绝缘体区域从管芯中的电路耦合并用于分析管芯。材料沉积在暴露的区域中，并且已经去除的模具的选定部分被重建。重建在信号耦合之前，期间或之后进行，这取决于正在分析的管芯和正在执行的分析的类型。以这种方式，通过能够通过绝缘体耦合信号并修复已经被改变以用于分析的芯片的一部分的能力来提高用于分析芯片的访问。否则可以进行破坏性的分析，可以保持分析后的模具功能的能力。

3. 发明授权

US06850081B1 Semiconductor die analysis via fiber optic communication 失效
标题翻译：通过光纤通信进行半导体芯片分析
公开(公告)号：US06850081B1
公开(公告)日：2005-02-01
申请号：US10164506
申请日：2002-06-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： G01R31/28 , G01R31/319 , G01R31/303
CPC分类号： G01R31/2884 , G01R31/31905
摘要： Semiconductor analysis is improved via the use of fiber optic communications. According to an example embodiment of the present invention, a stimulation device is adapted to stimulate an integrated circuit die, and the die generates a response to the stimulation. An optical signal generator, either incorporated into the die or coupled to the die, detects the response, converts the response to an optical signal and transmits the optical signal. The optical signal is received at a testing arrangement adapted to analyze the die therefrom. The optical signal is used to analyze the die, improving signal quality and the ability to perform high-speed analysis of the die.
摘要翻译：通过使用光纤通信改进了半导体分析。根据本发明的示例性实施例，刺激装置适于刺激集成电路管芯，并且管芯产生对刺激的响应。将光信号发生器并入芯片或耦合到管芯，检测响应，将响应转换为光信号并发送光信号。光学信号在适于从其分析模具的测试装置处被接收。光信号用于分析芯片，提高信号质量和对芯片进行高速分析的能力。

4. 发明授权

US06414335B1 Selective state change analysis of a SOI die 失效
标题翻译： SOI裸片的选择状态变化分析
公开(公告)号：US06414335B1
公开(公告)日：2002-07-02
申请号：US09864688
申请日：2001-05-23
申请人： Rama R. Goruganthu , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone , Jeffrey D. Birdsley
发明人： Rama R. Goruganthu , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone , Jeffrey D. Birdsley
IPC分类号： H01L2358
CPC分类号： G01R31/312 , G01R31/307
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.
摘要翻译：通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

5. 发明授权

US06576484B1 IC die analysis via back side circuit construction with heat dissipation 失效
标题翻译： IC芯片分析通过背面电路结构散热
公开(公告)号：US06576484B1
公开(公告)日：2003-06-10
申请号：US09864668
申请日：2001-05-23
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2100
CPC分类号： H01L23/3735 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled. The back side circuitry is operated in conjunction with the circuit side circuitry during testing and operation, and is useful, for example, for replacing defective circuitry, modifying circuit operation, and/or providing stimuli to the circuit side circuitry. The thermal conductivity enhancing material dissipates the heat generated by the circuitry and reduces the risk of a thermal related breakdown of the die. This improves the ability to analyze the die under normal and above normal operating temperatures without necessarily causing a failure in the die.
摘要翻译：使用用于提高半导体管芯的散热特性的系统和方法来增强半导体分析。根据本发明的示例性实施例，形成具有在后侧相反的电路侧中的电路的倒装芯片集成电路管芯，其背面包括导热性增强材料。导热性提高材料提高了操作和测试期间模具的散热特性，有助于减少或防止过热。在外侧形成硅的外延层，在外延层中构成电路。电路侧的预先存在的电路和后侧的新形成的电路电耦合。在测试和操作期间，背面电路与电路侧电路一起操作，并且例如用于替换有缺陷的电路，修改电路操作和/或向电路侧电路提供刺激是有用的。热导率增强材料消散了电路产生的热量，并降低了模具的热相关破坏的风险。这提高了在正常和高于正常操作温度下分析模具的能力，而不一定导致模具故障。

6. 发明授权

US06518783B1 Circuit construction in back side of die and over a buried insulator 失效
标题翻译：模具背面的电路结构和埋地绝缘子上方
公开(公告)号：US06518783B1
公开(公告)日：2003-02-11
申请号：US09864669
申请日：2001-05-23
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone , Rama R. Goruganthu
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone , Rama R. Goruganthu
IPC分类号： H01L2166
CPC分类号： G01R31/2884
摘要： According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of the bulk silicon layer on the back side is removed and a void created. A circuit is formed in the void and is coupled to the existing circuitry on the circuit side of the die. The new circuit is used to analyze the die during operation, testing, or other conditions. The newly formed circuit enhances the ability to analyze the semiconductor die by adding flexibility to the traditional analysis methods used for integrated circuit dice. The newly formed circuit enables many new ways of interactively using the existing circuitry some of which include replacement of defective circuitry, modification of existing circuit operations, and stimulation of existing circuitry for testing.
摘要翻译：根据本发明的示例性实施例，选择性地减薄在电路侧和背面之间具有掩埋绝缘体层的半导体管芯。在减薄期间，去除背面上的体硅层的选定部分并产生空隙。在空隙中形成电路并且耦合到管芯电路侧上的现有电路。新电路用于在运行，测试或其他条件下对芯片进行分析。新形成的电路通过增加集成电路芯片的传统分析方法的灵活性，增强了半导体芯片的分析能力。新形成的电路使得能够交互地使用现有电路的许多新方式，其中一些电路包括有缺陷电路的更换，现有电路操作的修改和用于测试的现有电路的刺激。

7. 发明授权

US07019511B1 Optical analysis of integrated circuits 失效
标题翻译：集成电路的光学分析
公开(公告)号：US07019511B1
公开(公告)日：2006-03-28
申请号：US09755008
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： G01J5/02 , G01R31/00 , G01R31/302
CPC分类号： G01R31/311 , G01N21/1717 , G01N21/9501 , G01N2021/1721 , G01R31/304
摘要： The invention is directed to a system and method for analyzing an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, an optical beam arrangement is adapted to direct a modulated beam at a selected portion of the integrated circuit. The beam is sufficiently modulated to inhibit optical beam intrusion on the structure and operation of the integrated circuit. A reflected optical waveform response is obtained from the SOI selected portion. The inhibition of optical beam intrusion enhances the ability to analyze integrated circuits using an optical beam, making possible the use of analysis methods that otherwise would be difficult or even impossible to use.
摘要翻译：本发明涉及用于分析具有绝缘体上硅（SOI）结构的集成电路的系统和方法。根据本发明的一个示例性实施例，光束装置适于将调制束指向集成电路的选定部分。光束被充分调制，以阻止光束入射到集成电路的结构和操作上。从SOI选择部分获得反射光波形响应。光束入侵的抑制增强了使用光束分析集成电路的能力，使得可能使用否则将难以甚至不可能使用的分析方法。

8. 发明授权

US06621281B1 SOI die analysis of circuitry logic states via coupling through the insulator 有权
标题翻译：通过绝缘体耦合的电路逻辑状态的SOI裸片分析
公开(公告)号：US06621281B1
公开(公告)日：2003-09-16
申请号：US09755012
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Brennan V. Davis , Daniel L. Stone , Michael R. Bruce , Rosalinda M. Ring
发明人： Jeffrey D. Birdsley , Brennan V. Davis , Daniel L. Stone , Michael R. Bruce , Rosalinda M. Ring
IPC分类号： G01R3102
CPC分类号： G01R31/307
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.
摘要翻译：具有绝缘体上硅（SOI）结构的半导体管芯的分析通过从背面访问管芯内的电路而不破坏SOI结构的薄绝缘体层来增强。根据示例性实施例，从电路侧具有SOI结构和背面相反电路的半导体管芯的背面去除衬底的一部分。通过电容耦合装置对管芯内的电路的一部分进行电连接。电连接用于获得与用于分析的管芯的电路逻辑状态相关的电测量。

9. 发明授权

US06500699B1 Test fixture for future integration 失效
标题翻译：测试夹具，以便将来整合
公开(公告)号：US06500699B1
公开(公告)日：2002-12-31
申请号：US09613667
申请日：2000-07-11
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2150
CPC分类号： G01R31/2831 , G01R31/2853 , G01R31/2886 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： According to one aspect of the disclosure, the present invention provides methods and arrangements for testing a flip chip SOI semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For some chips, thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a special test fixture having a passive, corrosion-resistant heat-dissipating device is arranged to draw heat from the device.
摘要翻译：根据本公开的一个方面，本发明提供了在芯片的背面已经变薄以暴露衬底中的选定区域之后测试倒装芯片SOI半导体器件的方法和布置。对于某些芯片，当电路以高速运行时，薄化可去除用于从内部电路吸走热量的衬底材料。为了补偿这种材料损失，设置了具有被动耐腐蚀的散热装置的特殊测试夹具来从装置抽取热量。

10. 发明授权

US06403388B1 Nanomachining method for integrated circuits 失效
标题翻译：集成电路的纳米加工方法
公开(公告)号：US06403388B1
公开(公告)日：2002-06-11
申请号：US09755005
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： H01L2166
CPC分类号： G01R31/316 , G01R31/311 , Y10S438/967 , Y10S438/977
摘要： A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.
摘要翻译：一种系统和方法提供了对具有绝缘体上硅（SOI）结构的集成电路的有效分析。根据本发明的一个示例性实施例，该系统包括适于去除具有SOI结构的半导体器件的背面的选定部分的系统（例如，纳米加工布置），并且将所选择的电路部分电隔离 SOI半导体器件电路侧。然后分析隔离电路。

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