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1. 发明申请

US20120207920A1 PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WITH A PLURALITY OF MOLD CAVITIES 失效
标题翻译：保护拥有大量模具CAE的大型平面表面的模具
公开(公告)号：US20120207920A1
公开(公告)日：2012-08-16
申请号：US13453371
申请日：2012-04-23
申请人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
发明人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
IPC分类号： B28B7/34
CPC分类号： H01L24/742 , H01L24/11 , H01L24/13 , H01L2224/11003 , H01L2224/131 , H01L2924/1431 , H01L2924/15788 , H01L2924/181 , H05K3/3478 , H01L2924/014 , H01L2924/00
摘要： A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.
摘要翻译：一种保护模具的方法，该模具具有设置有多个模腔的至少一个基本平坦的表面，包括将多个心轴插入到多个模腔中的相应的模腔中，将一层模具保护材料沉积在至少一个基本平面表面和多个心轴，并且从模具基板移除多个心轴。

2. 发明授权

US08668834B2 Protecting a mold having a substantially planar surface provided with a plurality of mold cavities 失效
标题翻译：保护具有设置有多个模腔的基本平坦的表面的模具
公开(公告)号：US08668834B2
公开(公告)日：2014-03-11
申请号：US13453371
申请日：2012-04-23
申请人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
发明人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
IPC分类号： C25F3/00 , B28B7/38
CPC分类号： H01L24/742 , H01L24/11 , H01L24/13 , H01L2224/11003 , H01L2224/131 , H01L2924/1431 , H01L2924/15788 , H01L2924/181 , H05K3/3478 , H01L2924/014 , H01L2924/00
摘要： A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.
摘要翻译：一种保护模具的方法，该模具具有设置有多个模腔的至少一个基本平坦的表面，包括将多个心轴插入到多个模腔中的相应的模腔中，将一层模具保护材料沉积在至少一个基本平面表面和多个心轴，并且从模具基板移除多个心轴。

3. 发明申请

US20110079702A1 FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE LAYER 审中-公开
标题翻译：在保护层模具和模具上形成保护层
公开(公告)号：US20110079702A1
公开(公告)日：2011-04-07
申请号：US12573904
申请日：2009-10-06
申请人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
发明人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
IPC分类号： B28B7/36 , B28B7/38 , B44C1/22
CPC分类号： H01L24/742 , H01L24/11 , H01L24/13 , H01L2224/11003 , H01L2224/131 , H01L2924/1431 , H01L2924/15788 , H01L2924/181 , H05K3/3478 , H01L2924/014 , H01L2924/00
摘要： A method of forming a mold having a protective layer includes forming a mold substrate having at least one substantially planar surface, depositing a layer of mold protection material onto the at least one substantially planar surface, and etching a plurality of cavities into the at least one substantially planar surface through the mold protection layer.
摘要翻译：一种形成具有保护层的模具的方法包括形成具有至少一个基本平坦的表面的模具基底，将一层模具保护材料沉积在所述至少一个基本平坦的表面上，以及将多个模腔蚀刻成至少一个基本平坦的表面通过模具保护层。

4. 发明授权

US07572726B2 Method of forming a bond pad on an I/C chip and resulting structure 有权
标题翻译：在I / C芯片上形成接合焊盘的方法和结构
公开(公告)号：US07572726B2
公开(公告)日：2009-08-11
申请号：US11271760
申请日：2005-11-10
申请人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
发明人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要翻译：一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。在衬垫的暴露表面和开口表面上形成至少第一导电层。在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。本发明还包括所得到的结构。

5. 发明授权

US06995475B2 I/C chip suitable for wire bonding 有权
标题翻译： I / C芯片适用于引线键合
公开(公告)号：US06995475B2
公开(公告)日：2006-02-07
申请号：US10666775
申请日：2003-09-18
申请人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
发明人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要翻译：一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。在衬垫的暴露表面和开口表面上形成至少第一导电层。在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。本发明还包括所得到的结构。

6. 发明申请

US20090181533A1 ALIGNMENT VERIFICATION FOR C4NP SOLDER TRANSFER 失效
标题翻译： C4NP焊接传输的对准验证
公开(公告)号：US20090181533A1
公开(公告)日：2009-07-16
申请号：US11954828
申请日：2007-12-12
申请人： Jerry A. Gorrell , Sarah H. Knickerbocker , Srinivasa S.N. Reddy
发明人： Jerry A. Gorrell , Sarah H. Knickerbocker , Srinivasa S.N. Reddy
IPC分类号： H01L21/441
CPC分类号： H05K3/3457 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/11334 , H01L2224/13099 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K2203/0113 , H05K2203/0338 , H01L2224/29099 , H01L2224/05599
摘要： A method is provided for the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and determines if any off-set resulted between the solder mold array and the wafer capture array during the transfer process. The amount of off-set enables the operator to adjust the transfer tool before solder transfer to compensate for the off-set caused by the transfer process and provides a more cost-effective and efficient solder transfer process. A solder reactive material surrounding the capture pads is used to determine where the solder reacts with the solder reactive material showing the off-set resulting from the transfer process. Copper is a preferred solder reactive material.
摘要翻译：提供了一种用于在晶片或其他电子设备上制造互连焊料凸块的方法。该方法对于众所周知的C4NP互连技术特别有用，并且确定在传输过程期间在焊料模具阵列和晶片捕获阵列之间是否产生偏移。偏移量使操作员能够在焊接传输之前调整传送工具，以补偿由传送过程引起的偏移，并提供更具成本效益和更有效的焊接传输过程。使用围绕捕获垫的焊料反应性材料来确定焊料与焊料反应性材料反应的位置，显示由转移过程导致的偏移。铜是优选的焊料反应性材料。

7. 发明授权

US5541005A Large ceramic article and method of manufacturing 失效
标题翻译：大型陶瓷制品及其制造方法
公开(公告)号：US5541005A
公开(公告)日：1996-07-30
申请号：US438825
申请日：1995-05-11
申请人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人： Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katherine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sarah H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号： B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/105
CPC分类号： H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要： A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译：一种用于电子应用的大型陶瓷衬底制品，包括至少一层烧结陶瓷材料，该层包括多个边缘到边缘连接的陶瓷材料毛坯块。还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。

8. 发明授权

US5277725A Process for fabricating a low dielectric composite substrate 失效
标题翻译：低介电复合衬底的制造方法
公开(公告)号：US5277725A
公开(公告)日：1994-01-11
申请号：US881448
申请日：1992-05-11
申请人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
发明人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
IPC分类号： H05K1/03 , C04B41/48 , C04B41/49 , H01L21/48 , H01L23/08 , H01L23/538 , H05K3/40 , C04B37/00 , B05D5/12
CPC分类号： H01L21/4857 , C04B41/488 , C04B41/4961 , H01L23/5383 , H05K3/4061 , C04B2111/00672 , C04B2111/00844 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K1/0306 , H05K2201/09581 , H05K2203/1147 , H05K2203/308
摘要： The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.
摘要翻译：在金属的热循环过程中经历的裂纹：电介质半导体封装是由热膨胀系数不匹配引起的。与这种开裂相关的非气密性可以通过用柔性材料回填可渗透裂缝来解决。金属和电介质材料之间的均匀间隙可以类似地填充柔性材料，以提供应力消除，体积可压缩性和包装的强度。此外，可渗透的骨架电介质可以被制造为具有烧结冶金的烧结多层结构，并随后注入柔性的温度稳定的材料以提供气密性和强度。

9. 发明授权

US08753460B2 Reduction of edge chipping during wafer handling 有权
标题翻译：在晶片处理期间减少边缘切屑
公开(公告)号：US08753460B2
公开(公告)日：2014-06-17
申请号：US13015638
申请日：2011-01-28
申请人： Sarah H. Knickerbocker , Jonathan H. Griffith
发明人： Sarah H. Knickerbocker , Jonathan H. Griffith
IPC分类号： B32B37/02
CPC分类号： H01L21/6835 , H01L2221/68327
摘要： Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.
摘要翻译：公开了用于加强结合到载体的半导体晶片的周边的方法和系统。在一个实施例中，在粘合之前将另外的粘合剂施加到半导体晶片。附加的粘合剂渗入载体和晶片之间的缝隙并提供增强。在另一个实施例中，在将晶片结合到玻璃载体上之后，通过分配器将粘合剂施加到缝隙。

10. 发明授权

US07737003B2 Method and structure for optimizing yield of 3-D chip manufacture 有权
标题翻译：优化3-D芯片制造产量的方法和结构
公开(公告)号：US07737003B2
公开(公告)日：2010-06-15
申请号：US11163226
申请日：2005-10-11
申请人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
发明人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
IPC分类号： H01L21/00
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/13
摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
摘要翻译：该过程开始于具有互补芯片的单独的器件晶片。薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。捕获垫被去除并在变薄后更换。切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。具有已知良好3-D芯片的器件晶片然后进行最终处理。

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