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1. 发明授权

US07523434B1 Interfacing with a dynamically configurable arithmetic unit 有权
标题翻译：与动态配置的运算单元接口
公开(公告)号：US07523434B1
公开(公告)日：2009-04-21
申请号：US11234490
申请日：2005-09-23
申请人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
发明人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for proper syntax and one or more abstract syntax trees can be formed. Next, the input variables are then assigned to input ports of the dynamically configurable arithmetic unit. Then using the parsed mathematical expressions with the assigned input ports, a list of operations to be performed by the dynamically configurable arithmetic unit are determined. And lastly, an interface to the dynamically configurable arithmetic unit is generated using in part the variable-to-input port assignments and the list of operations.
摘要翻译：示例性实施例包括接收具有多个输入变量的多个数学表达式的方法。然后可以解析数学表达式，检查正确的语法，并且可以形成一个或多个抽象语法树。接下来，将输入变量分配给动态配置的运算单元的输入端口。然后使用已分配的输入端口的解析数学表达式，确定要由动态配置的运算单元执行的操作列表。最后，使用部分变量输入端口分配和操作列表来生成动态配置的运算单元的接口。

2. 发明授权

US08024678B1 Interfacing with a dynamically configurable arithmetic unit 有权
标题翻译：与动态配置的运算单元接口
公开(公告)号：US08024678B1
公开(公告)日：2011-09-20
申请号：US12416333
申请日：2009-04-01
申请人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
发明人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.
摘要翻译：动态配置的算术单元的接口可以包括数据对准模块，其中每个数据对准模块接收与一个或多个算术表达式相关联的输入变量。接口可以包括耦合到数据对准模块的多路复用器，其中数据对准模块具有耦合到第一多路复用器的输出。第一复用器可以具有选择线和耦合到可动态配置的运算单元的输入端口的输出。接口可以包括具有输入指令和选择线的第二多路复用器，其中每个指令与算术表达式中的一个相关联，并且具有由可动态配置的运算单元执行的操作。第二多路复用器可配置成通过第二多路复用器的输出将响应于选择线的输入指令的选定输入指令提供给动态可配置的运算单元。

3. 发明授权

US07571395B1 Generation of a circuit design from a command language specification of blocks in matrix form 有权
标题翻译：从矩阵形式的块的命令语言规范生成电路设计
公开(公告)号：US07571395B1
公开(公告)日：2009-08-04
申请号：US11196174
申请日：2005-08-03
申请人： Shay Ping Seng , Arvind Sundararajan
发明人： Shay Ping Seng , Arvind Sundararajan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of the instances of design blocks are established in the memory arrangement in response to at least one user-entered command that specifies respective matrix positions of the instances. Representative connections between the instances are generated in the memory arrangement in response to a user-entered command having no specification of the connections.
摘要翻译：使用命令语言生成电路设计。各种方法包括响应于指定实例的创建的用户输入的命令，在存储器布置中生成设计块的各个实例。响应于指定实例的各个矩阵位置的至少一个用户输入的命令，在存储器装置中建立设计块的实例的矩阵相对位置。这些实例之间的代表性连接响应于没有指定连接的用户输入的命令而在存储器装置中产生。

4. 发明授权

US08015537B1 Automated rate realization for circuit designs within high level circuit implementation tools 有权
标题翻译：高级电路实现工具中电路设计的自动速率实现
公开(公告)号：US08015537B1
公开(公告)日：2011-09-06
申请号：US12468640
申请日：2009-05-19
申请人： Arvind Sundararajan , Nabeel Shirazi
发明人： Arvind Sundararajan , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.
摘要翻译：用于实现可编程集成电路内的电路设计的计算机实现的方法可以包括将电路设计的时钟域的数据速率与电路设计的可用时钟源的频率进行比较，并确定哪些时钟域具有数据速率匹配时钟源的频率。对于具有与时钟源频率匹配的数据速率的每个时钟域，时钟域的负载可以使用具有匹配时钟源的多个同步时钟技术来计时。对于具有与时钟源的频率不匹配的数据速率的每个时钟域，时钟域的负载可以使用时钟使能技术来计时。可以输出指定每个时钟域的时钟电路的电路设计。

5. 发明授权

US07933900B2 Search over structured data 有权
标题翻译：搜索结构化数据
公开(公告)号：US07933900B2
公开(公告)日：2011-04-26
申请号：US11257282
申请日：2005-10-23
申请人： Bindu Reddy , Jonathan Brunsman , Ning Mosberger , Gaurav Ravindra Bhaya , Sarah Sirajuddin , David Kale , Jennifer L. Kozenski , Arvind Sundararajan , Puneet Agarwal
发明人： Bindu Reddy , Jonathan Brunsman , Ning Mosberger , Gaurav Ravindra Bhaya , Sarah Sirajuddin , David Kale , Jennifer L. Kozenski , Arvind Sundararajan , Puneet Agarwal
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30867 , G06F17/30017 , G06F17/3012 , G06F17/30312 , G06F17/30424 , G06F17/30864 , G06F17/30893
摘要： A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.
摘要翻译：用户可以通过指定使用标签或属性值来进一步过滤查询结果来优化对结构化数据的搜索。

6. 发明授权

US08762372B2 Search over structured data 有权
标题翻译：搜索结构化数据
公开(公告)号：US08762372B2
公开(公告)日：2014-06-24
申请号：US13092203
申请日：2011-04-22
申请人： Bindu Reddy , Lawrence J. Brunsman , Ning Mosberger , Gaurav Ravindra Bhaya , Sarah Sirajuddin , David Kale , Jennifer L. Kozenski , Arvind Sundararajan , Puneet Agarwal
发明人： Bindu Reddy , Lawrence J. Brunsman , Ning Mosberger , Gaurav Ravindra Bhaya , Sarah Sirajuddin , David Kale , Jennifer L. Kozenski , Arvind Sundararajan , Puneet Agarwal
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30867 , G06F17/30017 , G06F17/3012 , G06F17/30312 , G06F17/30424 , G06F17/30864 , G06F17/30893
摘要： A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.
摘要翻译：用户可以通过指定使用标签或属性值来进一步过滤查询结果来优化对结构化数据的搜索。

7. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

8. 发明授权

US08650019B1 Linking untimed data-path and timed control-path models 有权
标题翻译：链接未定义的数据路径和定时控制路径模型
公开(公告)号：US08650019B1
公开(公告)日：2014-02-11
申请号：US12695800
申请日：2010-01-28
申请人： Arvind Sundararajan , Chi Bun Chan
发明人： Arvind Sundararajan , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Approaches for creating a timed hybrid simulation model for a circuit design specification. An untimed, high-level language (HLL) data-path model is input, along with an HLL data-path interface specification that specifies input ports of the HLL data-path model. A hardware description language (HDL) control-path model that specifies port attributes and associated stitching directives is generated. Each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model. The HLL data-path and HDL control-path models are linked (314) to create the timed hybrid simulation model, and the timed hybrid simulation model is stored in a processor-readable storage medium.
摘要翻译：为电路设计规范创建定时混合仿真模型的方法。输入未定义的高级语言（HLL）数据路径模型，以及指定HLL数据路径模型的输入端口的HLL数据路径接口规范。生成指定端口属性和关联拼接指令的硬件描述语言（HDL）控制路径模型。每个拼接指令指定HLL数据路径模型的控制端口和关联的一个输入端口。将HLL数据路径和HDL控制路径模型链接（314）以创建定时混合仿真模型，并将定时混合仿真模型存储在处理器可读存储介质中。

9. 发明授权

US08417965B1 Method and circuit for secure definition and integration of cores 有权
标题翻译：核心的安全定义和集成的方法和电路
公开(公告)号：US08417965B1
公开(公告)日：2013-04-09
申请号：US12755760
申请日：2010-04-07
申请人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
发明人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , G06F9/445 , H04L29/06 , H04L9/00 , H04L9/30 , H04K1/00 , H04N7/16
CPC分类号： G06F17/505 , G06F11/3664 , G06F17/5054 , H04L9/0825 , H04L9/0877 , H04L63/0478
摘要： An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
摘要翻译：本发明的一个实施例提供了一种用于将核心安全地定义和集成到电路设计中而不暴露核心的方法和电路。在一个实施例中，获得核心开发包。核心开发包包括加密核心和加密核心的解密密钥。解密密钥用非对称密码加密。加密核心从设计工具传输到可信平台模块。解密密钥用非对称密码的私钥解密。加密核心在可信平台模块内被解密。使用解密的核执行一个或多个设计工具操作。

10. 发明授权

US08042079B1 Synchronization for a modeling system 有权
标题翻译：建模系统的同步
公开(公告)号：US08042079B1
公开(公告)日：2011-10-18
申请号：US12468764
申请日：2009-05-19
申请人： Arvind Sundararajan , Haibing Ma , Andrew Dow , Singh Vinay Jitendra
发明人： Arvind Sundararajan , Haibing Ma , Andrew Dow , Singh Vinay Jitendra
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.
摘要翻译：描述了集成电路设备（“IC”）的高级建模系统（“HLMS”）的设计同步。在用于生成网表的方法中，将用户设计的第一电路块的描述输入到用计算机辅助建模系统编程的编程计算机系统。该描述包括第一电路块的输出端口信息和同步信号信息。计算机辅助建模系统响应于输出端口信息和同步信号信息，电路核心包括端口元数据，为第一电路块选择电路核心。计算机辅助建模系统响应于端口元数据选择至少一个宏来生成网表。该宏是用于将第一电路块与用户设计的第二电路块的速率同步耦合。计算机辅助建模系统输出包含宏的网表。

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