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1. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

2. 发明授权

US08402442B1 Common debugger method and system 有权
标题翻译：常用的调试器方法和系统
公开(公告)号：US08402442B1
公开(公告)日：2013-03-19
申请号：US12510810
申请日：2009-07-28
申请人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/267 , G06F11/3664
摘要： Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.
摘要翻译：公开了用于操作多个调试器工具的方法。一个常见的调试器接收第一个类型的命令进行处理。每个first-type命令引用一个调试器工具。每个调试器工具提供对电子系统的一个或多个组件的相应集合的控制，并识别相应的一组工具特定命令。每个输入第一类型命令被转换成与第一类型命令中指定的调试器工具兼容的相应的特定于工具的命令。来自公共调试器的每个相应的特定于工具的命令被提供给转换相应的特定于工具的命令的输入第一类型命令中指定的调试器工具之一。每个翻译的特定于工具的命令都由目标调试工具执行。

3. 发明授权

US08620638B1 Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design 有权
标题翻译：执行被测设计的仿真的方法和用于实现电路设计测试的电路
公开(公告)号：US08620638B1
公开(公告)日：2013-12-31
申请号：US12335025
申请日：2008-12-15
申请人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5022
摘要： A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.
摘要翻译：公开了一种对被测设计进行仿真的方法。该方法包括实现具有可调输出宽度的输入块; 将测试数据耦合到输入块; 根据输入块的被测设计的输入要求，生成包含被测设计的测试数据的输入信号; 实现具有可调输入宽度的输出块，用于从被测设计的输出接收数据; 并根据被测设计的输出要求将被测设计的输出耦合到输出块。还公开了一种能够测试在集成电路中实现的电路设计的电路。

4. 发明授权

US08352229B1 Reloadable just-in-time compilation simulation engine for high level modeling systems 有权
标题翻译：用于高级建模系统的可重新加载的即时编译仿真引擎
公开(公告)号：US08352229B1
公开(公告)日：2013-01-08
申请号：US12359409
申请日：2009-01-26
申请人： Haibing Ma , Chi Bun Chan , Jingzhao Ou
发明人： Haibing Ma , Chi Bun Chan , Jingzhao Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F9/4552
摘要： A computer-implemented method of creating a simulation engine for simulating a circuit design can include receiving a source code contribution from a high level modeling system and receiving a simulation model specified in an interpretive language that specifies the circuit design. The source code contribution can be compiled together with the simulation model using a Just-In-Time compiler. A simulation engine, specified in native machine code, can be output as a single, integrated software component formed from the source code contribution and the simulation model.
摘要翻译：用于创建用于模拟电路设计的模拟引擎的计算机实现的方法可以包括从高级建模系统接收源代码贡献，并且接收指定电路设计的解释语言中指定的仿真模型。可以使用即时编译器将源代码贡献与仿真模型一起编译。以本机代码指定的模拟引擎可以作为由源代码贡献和仿真模型组成的单一的集成软件组件输出。

5. 发明授权

US08332786B1 High level system design using functional and object-oriented composition 有权
标题翻译：使用功能和面向对象组合的高级系统设计
公开(公告)号：US08332786B1
公开(公告)日：2012-12-11
申请号：US12697881
申请日：2010-02-01
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a high level modeling system (HLMS) comprising a processor and a memory, a method can include executing a system template comprising a plurality of modules of an electronic system, wherein each module represents a hardware component of the electronic system and is specified in the form of an extendable, higher order function, and extending, during runtime, a first module of the plurality of modules with a first extension by binding, via the processor, the first extension to the first module. The plurality of modules comprising the first extension to the first module can be stored within the memory.
摘要翻译：在包括处理器和存储器的高级建模系统（HLMS）中，方法可以包括执行包括电子系统的多个模块的系统模板，其中每个模块表示电子系统的硬件组件，并且在形式的可扩展，高阶功能，并且在运行时间期间通过经由处理器将第一扩展装置绑定到第一模块，借助于第一扩展来延伸多个模块中的第一模块。包括到第一模块的第一扩展的多个模块可以存储在存储器内。

6. 发明授权

US08145466B1 Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms 有权
标题翻译：用于基于硬件和基于软件的协同仿真平台的电子电路设计模块的集群
公开(公告)号：US08145466B1
公开(公告)日：2012-03-27
申请号：US12469897
申请日：2009-05-21
申请人： Chi Bun Chan , Jingzhao Ou , Haibing Ma , Shay P. Seng
发明人： Chi Bun Chan , Jingzhao Ou , Haibing Ma , Shay P. Seng
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.
摘要翻译：公开了制备电子电路仿真模型的方法。设计分为第一和第二集群。该设计包括在第一集群中连接到第二集群中的目标模块的源模块。第一个集群被编译成基于软件的协同仿真平台的第一个模型，用于使用第一个模型模拟源模块的行为。该设计的第一个集群和第二个集群被编译成一个基于硬件的协同仿真平台的第二个模型，该平台包括一个可编程逻辑电路，可配置为使用第二个模型模拟设计的行为。生成互连块并将其存储在第二模型中。互连块可在第二模型中的目的地模块与第一模型的源模块耦合到第二模型的源模块之间切换。

7. 发明授权

US08041855B1 Dual-bus system for communicating with a processor 有权
标题翻译：双总线系统，用于与处理器通信
公开(公告)号：US08041855B1
公开(公告)日：2011-10-18
申请号：US12360764
申请日：2009-01-27
申请人： Jingzhao Ou , Chi Bun Chan
发明人： Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F3/00 , G06F13/28 , G06F13/00 , G06F13/36
CPC分类号： G06F13/28
摘要： A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bus adapter further can be coupled to a memory map interface (135) through which at least one peripheral device communicates with the processor. Single word operations can be exchanged between the processor and the dual-bus adapter through the first communication channel. Burst transfer operations can be performed by exchanging signaling information between the processor and the dual-bus adapter over the first communication channel and exchanging data words between the processor and the dual-bus adapter through the second communication channel.
摘要翻译：用于与集成电路内的处理器通信的系统可以包括通过第一通信信道（110）和第二通信信道（120）耦合到处理器（105）的双总线适配器（115）。双总线适配器还可以耦合到存储器映射接口（135），至少一个外围设备通过该存储器映射接口与处理器进行通信。可以通过第一通信信道在处理器和双总线适配器之间交换单字操作。可以通过在第一通信信道上通过在处理器和双总线适配器之间交换信令信息并通过第二通信信道在处理器和双总线适配器之间交换数据字来执行突发传送操作。

8. 发明授权

US08248869B1 Configurable memory map interface and method of implementing a configurable memory map interface 有权
标题翻译：可配置的存储器映射接口和实现可配置存储器映射接口的方法
公开(公告)号：US08248869B1
公开(公告)日：2012-08-21
申请号：US12581099
申请日：2009-10-16
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： G11C7/00
CPC分类号： G06F12/0646 , G11C7/1009 , G11C7/1012 , G11C2029/1806 , G11C2029/5602
摘要： A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.
摘要翻译：公开了一种耦合到具有输入/输出端口的电路元件的可配置存储器映射接口。可配置存储器映射接口包括耦合以接收能够读取或写入电路元件的地址的输入; 存储器使能信号参数的存储器，所述使能信号参数控制用于从所述电路元件读取或写入所述电路元件的使能信号的定时; 以及使能信号发生器，其基于存储在存储器中的使能信号参数，产生使能信号，使得能够读取或写入电路元件。还公开了一种实现可配置存储器映射接口的方法。

9. 发明授权

US07992111B1 Conversion of a high-level graphical circuit design block to a high-level language program 有权
标题翻译：将高级图形电路设计块转换为高级语言程序
公开(公告)号：US07992111B1
公开(公告)日：2011-08-02
申请号：US12467678
申请日：2009-05-18
申请人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
发明人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F9/45
CPC分类号： G06F8/34
摘要： Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.
摘要翻译：处理电子电路设计的方法。在一个实施例中，外部子系统块和内部子系统块的图形模型被转换为高级语言（HLL）程序。 HLL程序包括与外部子系统块相对应的第一功能的规范，并且在第一功能的规范内包括对应于内部子系统块的第二功能的规范。第一个函数的规范引用外部子系统块的参数，并指定第二个函数的调用。第二函数的规范规定了对应于内子系统块中的叶块的第三函数的调用。第一个函数的规范引用与参数对应的变量，该变量由第二或第三个函数引用。执行HLL程序实例化设计模型。

10. 发明授权

US07930162B1 Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor 有权
标题翻译：使用先进先出驱动命令处理器的动态重放加速硬件协同仿真
公开(公告)号：US07930162B1
公开(公告)日：2011-04-19
申请号：US12115340
申请日：2008-05-05
申请人： Chi Bun Chan , Shay Ping Seng , Jingzhao Ou
发明人： Chi Bun Chan , Shay Ping Seng , Jingzhao Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.
摘要翻译：配置用于硬件协同仿真的集成电路可以包括命令处理器，存储命令模板的重放缓冲器，其中命令模板指定不完整的命令，以及存储用于完成的补充数据的先进先出（FIFO）存储器的命令模板。集成电路还可以包括耦合到命令处理器，重播缓冲器和命令FIFO的多路复用器。在命令处理器的控制下，多路复用器可以选择性地将数据从重播缓冲器或命令FIFO提供给命令处理器。命令处理器响应于在硬件协同仿真会话期间读取的重放命令，可以进入重放模式，从重播缓冲器获取命令模板，根据从命令模板读取的符号从FIFO存储器获取补充数据，并通过将命令模板与补充数据相加形成完整的命令。

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