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1. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

2. 发明授权

US08650019B1 Linking untimed data-path and timed control-path models 有权
标题翻译：链接未定义的数据路径和定时控制路径模型
公开(公告)号：US08650019B1
公开(公告)日：2014-02-11
申请号：US12695800
申请日：2010-01-28
申请人： Arvind Sundararajan , Chi Bun Chan
发明人： Arvind Sundararajan , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Approaches for creating a timed hybrid simulation model for a circuit design specification. An untimed, high-level language (HLL) data-path model is input, along with an HLL data-path interface specification that specifies input ports of the HLL data-path model. A hardware description language (HDL) control-path model that specifies port attributes and associated stitching directives is generated. Each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model. The HLL data-path and HDL control-path models are linked (314) to create the timed hybrid simulation model, and the timed hybrid simulation model is stored in a processor-readable storage medium.
摘要翻译：为电路设计规范创建定时混合仿真模型的方法。输入未定义的高级语言（HLL）数据路径模型，以及指定HLL数据路径模型的输入端口的HLL数据路径接口规范。生成指定端口属性和关联拼接指令的硬件描述语言（HDL）控制路径模型。每个拼接指令指定HLL数据路径模型的控制端口和关联的一个输入端口。将HLL数据路径和HDL控制路径模型链接（314）以创建定时混合仿真模型，并将定时混合仿真模型存储在处理器可读存储介质中。

3. 发明授权

US08417965B1 Method and circuit for secure definition and integration of cores 有权
标题翻译：核心的安全定义和集成的方法和电路
公开(公告)号：US08417965B1
公开(公告)日：2013-04-09
申请号：US12755760
申请日：2010-04-07
申请人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
发明人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , G06F9/445 , H04L29/06 , H04L9/00 , H04L9/30 , H04K1/00 , H04N7/16
CPC分类号： G06F17/505 , G06F11/3664 , G06F17/5054 , H04L9/0825 , H04L9/0877 , H04L63/0478
摘要： An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
摘要翻译：本发明的一个实施例提供了一种用于将核心安全地定义和集成到电路设计中而不暴露核心的方法和电路。在一个实施例中，获得核心开发包。核心开发包包括加密核心和加密核心的解密密钥。解密密钥用非对称密码加密。加密核心从设计工具传输到可信平台模块。解密密钥用非对称密码的私钥解密。加密核心在可信平台模块内被解密。使用解密的核执行一个或多个设计工具操作。

4. 发明授权

US08248869B1 Configurable memory map interface and method of implementing a configurable memory map interface 有权
标题翻译：可配置的存储器映射接口和实现可配置存储器映射接口的方法
公开(公告)号：US08248869B1
公开(公告)日：2012-08-21
申请号：US12581099
申请日：2009-10-16
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： G11C7/00
CPC分类号： G06F12/0646 , G11C7/1009 , G11C7/1012 , G11C2029/1806 , G11C2029/5602
摘要： A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.
摘要翻译：公开了一种耦合到具有输入/输出端口的电路元件的可配置存储器映射接口。可配置存储器映射接口包括耦合以接收能够读取或写入电路元件的地址的输入; 存储器使能信号参数的存储器，所述使能信号参数控制用于从所述电路元件读取或写入所述电路元件的使能信号的定时; 以及使能信号发生器，其基于存储在存储器中的使能信号参数，产生使能信号，使得能够读取或写入电路元件。还公开了一种实现可配置存储器映射接口的方法。

5. 发明授权

US07992111B1 Conversion of a high-level graphical circuit design block to a high-level language program 有权
标题翻译：将高级图形电路设计块转换为高级语言程序
公开(公告)号：US07992111B1
公开(公告)日：2011-08-02
申请号：US12467678
申请日：2009-05-18
申请人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
发明人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F9/45
CPC分类号： G06F8/34
摘要： Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.
摘要翻译：处理电子电路设计的方法。在一个实施例中，外部子系统块和内部子系统块的图形模型被转换为高级语言（HLL）程序。 HLL程序包括与外部子系统块相对应的第一功能的规范，并且在第一功能的规范内包括对应于内部子系统块的第二功能的规范。第一个函数的规范引用外部子系统块的参数，并指定第二个函数的调用。第二函数的规范规定了对应于内子系统块中的叶块的第三函数的调用。第一个函数的规范引用与参数对应的变量，该变量由第二或第三个函数引用。执行HLL程序实例化设计模型。

6. 发明授权

US07930162B1 Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor 有权
标题翻译：使用先进先出驱动命令处理器的动态重放加速硬件协同仿真
公开(公告)号：US07930162B1
公开(公告)日：2011-04-19
申请号：US12115340
申请日：2008-05-05
申请人： Chi Bun Chan , Shay Ping Seng , Jingzhao Ou
发明人： Chi Bun Chan , Shay Ping Seng , Jingzhao Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.
摘要翻译：配置用于硬件协同仿真的集成电路可以包括命令处理器，存储命令模板的重放缓冲器，其中命令模板指定不完整的命令，以及存储用于完成的补充数据的先进先出（FIFO）存储器的命令模板。集成电路还可以包括耦合到命令处理器，重播缓冲器和命令FIFO的多路复用器。在命令处理器的控制下，多路复用器可以选择性地将数据从重播缓冲器或命令FIFO提供给命令处理器。命令处理器响应于在硬件协同仿真会话期间读取的重放命令，可以进入重放模式，从重播缓冲器获取命令模板，根据从命令模板读取的符号从FIFO存储器获取补充数据，并通过将命令模板与补充数据相加形成完整的命令。

7. 发明授权

US07673201B1 Recovering a prior state of a circuit design within a programmable integrated circuit 有权
标题翻译：在可编程集成电路中恢复电路设计的先前状态
公开(公告)号：US07673201B1
公开(公告)日：2010-03-02
申请号：US12402728
申请日：2009-03-12
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： G01R31/28 , G06F7/38 , H03K19/00
CPC分类号： H03K19/17748 , G06F1/04 , G06F17/5054 , G06F2217/84 , H03K19/0016 , H03K19/1774 , H03K19/1776 , H03K19/17764
摘要： A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory. At a second simulation clock cycle, the clock of the circuit design can be gated. The stored configuration data can be loaded into configuration memory of the programmable IC, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle. The clock of the circuit design can be advanced a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle.
摘要翻译：恢复在可编程集成电路（IC）内实现的电路设计的选择的操作状态的方法可以包括流水线化选择性地暂停电路设计的时钟的时钟门控信号，以及存储指定电路设计的操作状态的配置数据在非配置存储器中的第一个模拟时钟周期。在第二个模拟时钟周期，电路设计的时钟可以选通。存储的配置数据可以被加载到可编程IC的配置存储器中，其中加载配置数据重新配置电路设计并且在第一仿真时钟周期恢复存在的电路设计的操作状态。电路设计的时钟可以提前多个时钟周期，对应于第二个模拟时钟周期和第一个仿真时钟周期之间的差异。

8. 发明授权

US08739088B1 Using constraints wtihin a high-level modeling system for circuit design 有权
标题翻译：在电路设计的高级建模系统中使用约束
公开(公告)号：US08739088B1
公开(公告)日：2014-05-27
申请号：US12581104
申请日：2009-10-16
申请人： Jingzhao Ou , Chi Bun Chan
发明人： Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/06
摘要： A computer implemented method for designing a circuit includes associating a high level design constraint with a first high level circuit component of a high level circuit design within a high level modeling system and translating the high level circuit design into a low level circuit design comprising at least one low level circuit component derived from the first high level circuit component. The method also includes automatically generating at least one low level design constraint from the high level design constraint for at least one low level circuit component and storing each low level design constraint in association with the low level circuit design.
摘要翻译：一种用于设计电路的计算机实现方法包括将高级设计约束与高级建模系统中的高级电路设计的第一高电平电路部件相关联，并将高电平电路设计转换成至少包括至少从第一高电平电路部件导出的一个低电平电路部件。该方法还包括从至少一个低电平电路部件的高电平设计约束中自动生成至少一个低电平设计约束，并且与低电平电路设计相关联地存储每个低电平设计约束。

9. 发明授权

US08402442B1 Common debugger method and system 有权
标题翻译：常用的调试器方法和系统
公开(公告)号：US08402442B1
公开(公告)日：2013-03-19
申请号：US12510810
申请日：2009-07-28
申请人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/267 , G06F11/3664
摘要： Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.
摘要翻译：公开了用于操作多个调试器工具的方法。一个常见的调试器接收第一个类型的命令进行处理。每个first-type命令引用一个调试器工具。每个调试器工具提供对电子系统的一个或多个组件的相应集合的控制，并识别相应的一组工具特定命令。每个输入第一类型命令被转换成与第一类型命令中指定的调试器工具兼容的相应的特定于工具的命令。来自公共调试器的每个相应的特定于工具的命令被提供给转换相应的特定于工具的命令的输入第一类型命令中指定的调试器工具之一。每个翻译的特定于工具的命令都由目标调试工具执行。

10. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

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