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1. 发明授权

US5017506A Method for fabricating a trench DRAM 失效
标题翻译：沟槽DRAM的制造方法
公开(公告)号：US5017506A
公开(公告)日：1991-05-21
申请号：US385344
申请日：1989-07-25
申请人： Bing-Whey Shen , Randy McKee , Gishi Chung
发明人： Bing-Whey Shen , Randy McKee , Gishi Chung
IPC分类号： H01L21/311 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L21/31116 , H01L27/10829 , Y10S438/948
摘要： The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. A DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells alows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistor of the memory cells.
摘要翻译：本发明的所述实施例提供了DRAM单元，结构和制造方法。制造具有沟槽电容器的DRAM单元，该沟槽电容器具有形成为在衬底中形成的沟槽的外表面上的扩散的第一板和形成在沟槽内的导电区域的第二板。转移晶体管使用场板隔离结构形成，该场板隔离结构包括用于转移晶体管的自对准的沟槽区域。护城河区域与电容器区域稍微重叠，并且允许增加的不对准公差，从而对DRAM单元的布局中内置的未对准公差的要求进行了前提。场板本身被蚀刻，使得其具有倾斜的侧壁，以避免由形成在集成电路上的后续导电层形成导电细丝。使用两个存储器单元之间的自对准位线接触，从而消除位线接触和存储器单元的传输晶体管的栅极之间的对准公差。

2. 发明授权

US4978634A Method of making trench DRAM cell with stacked capacitor and buried lateral contact 失效
标题翻译：制造具有堆叠电容器和埋入侧面接触的沟槽DRAM单元的方法
公开(公告)号：US4978634A
公开(公告)日：1990-12-18
申请号：US385327
申请日：1989-07-25
申请人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
发明人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861
摘要： The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.
摘要翻译：本发明的所述实施例提供了DRAM单元，结构和制造方法。在第一实施例中，制造具有沟槽电容器的DRAM单元，该沟槽电容器具有形成为在衬底中形成的沟槽的外表面上的扩散的第一板，以及形成在沟槽内部的导电区域的第二板。转移晶体管使用场板隔离结构形成，该场板隔离结构包括用于转移晶体管的自对准的沟槽区域。护城河区域与电容器区域稍微重叠，并且允许增加的不对准公差，从而对DRAM单元的布局中内置的未对准公差的要求进行了前提。场板本身被蚀刻，使得其具有倾斜的侧壁，以避免由形成在集成电路上的后续导电层形成导电细丝。使用两个存储单元之间的自对准位线接触允许消除位线接触和存储器单元的传输晶体管的栅极之间的对准公差。

3. 发明授权

US06893953B2 Fabrication process of a semiconductor device including a CVD process of a metal film 失效
标题翻译：包括金属膜的CVD工艺的半导体器件的制造工艺
公开(公告)号：US06893953B2
公开(公告)日：2005-05-17
申请号：US09835820
申请日：2001-04-17
申请人： Tomohisa Hoshino , Vincent Vezin , Gishi Chung
发明人： Tomohisa Hoshino , Vincent Vezin , Gishi Chung
IPC分类号： C25D7/12 , C23C16/02 , C23C16/56 , H01L21/28 , H01L21/285 , H01L21/311 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76862 , H01L21/2855 , H01L21/28556 , H01L21/31116 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： A method for fabricating a semiconductor device includes the steps of forming a barrier conductor layer on a substrate, exposing the barrier conductor layer to a first reducing gas atmosphere at an elevated substrate temperature, forming a metal film on the barrier conductor layer by a CVD process, and exposing the metal film to a second gas atmosphere at an elevated substrate temperature.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在衬底上形成阻挡导体层，在升高的衬底温度下将势垒导体层暴露于第一还原气体气氛，通过CVD工艺在阻挡导体层上形成金属膜并且在升高的基板温度下将金属膜暴露于第二气体气氛。

4. 发明申请

US20060037858A1 Electroless plating apparatus and electroless plating method 审中-公开
标题翻译：无电镀设备和化学镀方法
公开(公告)号：US20060037858A1
公开(公告)日：2006-02-23
申请号：US10528117
申请日：2003-05-23
申请人： Yoshinori Marumo , Miho Jomen , Takayuki Komiya , Hiroshi Sato , Gishi Chung
发明人： Yoshinori Marumo , Miho Jomen , Takayuki Komiya , Hiroshi Sato , Gishi Chung
IPC分类号： C25D17/06
CPC分类号： C23C18/1619 , C23C18/1669 , C23C18/1678
摘要： A plate is placed near a substrate held by a substrate holding section. A treating liquid is ejected from a treating liquid ejecting section, thereby plating the substrate electrolessly. The treating liquid flows through the gap between the substrate and the plate. Therefore a flow of the treating liquid occurs on the substrate. As a result, a fresh treating liquid can be supplied onto the substrate. Thus, a plating film can be formed very uniformly on the substrate even if the amount of treating liquid is small.
摘要翻译：将板放置在由基板保持部保持的基板附近。处理液从处理液喷射部喷出，由此无电解地镀覆基板。处理液体流过基板和板之间的间隙。因此，处理液的流动发生在基板上。结果，可以将新鲜的处理液体供应到基底上。因此，即使处理液的量少，也可以在基板上非常均匀地形成镀膜。

5. 发明授权

US06890869B2 Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof 失效
标题翻译：低电介质氮化硅膜及其制造方法，半导体器件及其制造方法
公开(公告)号：US06890869B2
公开(公告)日：2005-05-10
申请号：US10333683
申请日：2001-08-19
申请人： Gishi Chung
发明人： Gishi Chung
IPC分类号： C23C16/30 , C23C16/34 , H01L21/31 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/768 , H01L23/522 , H01L21/469
CPC分类号： H01L21/76834 , C23C16/345 , H01L21/0217 , H01L21/02222 , H01L21/02274 , H01L21/3125 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76813 , H01L21/76826 , H01L21/76829
摘要： A method of forming a silicon nitride film includes a CVD process that uses an organic Si compound having an organic silazane bond as a gaseous source. The CVD process is conducted under a condition that the organic silazane bond in the organic Si source is preserved in the silicon nitride film.
摘要翻译：形成氮化硅膜的方法包括使用具有有机硅氮烷键的有机Si化合物作为气态源的CVD工艺。在有机硅源中的有机硅氮烷键保存在氮化硅膜中的条件下进行CVD工艺。

6. 发明授权

US5352913A Dynamic memory storage capacitor having reduced gated diode leakage 失效
标题翻译：具有降低的门控二极管泄漏的动态存储器存储电容器
公开(公告)号：US5352913A
公开(公告)日：1994-10-04
申请号：US204909
申请日：1994-03-02
申请人： Gishi Chung , William R. McKee , Clarence W. Teng
发明人： Gishi Chung , William R. McKee , Clarence W. Teng
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10861 , H01L28/40
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。沟槽蚀刻成半导体材料体的表面。创建围绕沟槽的存储节点。在沟槽壁上形成多晶硅层。在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。还公开了沟槽型场板隔离随机存取存储单元结构。

7. 发明授权

US5252506A Method to eliminate gate filaments on field plate isolated devices 失效
标题翻译：在场板隔离装置上消除栅极细丝的方法
公开(公告)号：US5252506A
公开(公告)日：1993-10-12
申请号：US879697
申请日：1992-05-05
申请人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
发明人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
IPC分类号： H01L21/8242 , H01L21/306
CPC分类号： H01L27/10861
摘要： A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.
摘要翻译：公开了一种用于防止在诸如使用场板隔离的VLSI动态随机存取存储器的集成电路器件中形成不需要的多晶硅字线栅极细丝的方法。在处理字线之前，沿着场板开口的边缘在氮化物侧壁下方的场板开口中形成氧化物层。氧化物层部分地填充氮化物侧壁下方的浸渍下方的底切区域。去除氮化物侧壁的浸出。脱落区域的去除以及部分填充底切区域减少了当字线稍后添加时，多晶硅字线细丝在底切区域的场板开口的边缘周围形成的可能性。还公开了一种场板隔离存储器件，其中沿着场板开口的边缘，部分填充的氧化物层和侧壁氮化物层几乎重合。

8. 发明授权

US08394231B2 Plasma process device and plasma process method 有权
标题翻译：等离子体工艺装置和等离子体处理方法
公开(公告)号：US08394231B2
公开(公告)日：2013-03-12
申请号：US11656379
申请日：2007-01-23
申请人： Koichi Takatsuki , Hikaru Yoshitaka , Shigeo Ashigaki , Yoichi Inoue , Takashi Akahori , Shuuichi Ishizuka , Syoichi Abe , Takashi Suzuki , Kohei Kawamura , Hidenori Miyoshi , Gishi Chung , Yasuhiro Oshima , Hiroyuki Takahashi
发明人： Koichi Takatsuki , Hikaru Yoshitaka , Shigeo Ashigaki , Yoichi Inoue , Takashi Akahori , Shuuichi Ishizuka , Syoichi Abe , Takashi Suzuki , Kohei Kawamura , Hidenori Miyoshi , Gishi Chung , Yasuhiro Oshima , Hiroyuki Takahashi
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00 , H05H1/24 , H01J7/24
CPC分类号： H01J37/32009 , H01J37/3244 , H01J37/32541
摘要： That surface of an electrode plate 20 which is opposite to a susceptor 10 has a projection shape. The electrode plate 20 is fitted in an opening 26a of shield ring 26 at a projection 20a. At this time, the thickness of the projection 20a is approximately the same as the thickness of the shield ring 26. Accordingly, the electrode plate 20 and the shield ring 26 form substantially the same plane. The major surface of the projection 20a has a diameter 1.2 to 1.5 times the diameter of a wafer W. The electrode plate 20 is formed of, for example, SiC.
摘要翻译：与基座10相对的电极板20的表面具有突出形状。电极板20在突起20a处嵌合在屏蔽环26的开口26a中。此时，突起20a的厚度与屏蔽环26的厚度大致相同。因此，电极板20和屏蔽环26形成大致相同的平面。突起20a的主表面的直径为晶片W的直径的1.2〜1.5倍。电极板20例如由SiC形成。

9. 发明授权

US07662728B2 Substrate processing method 失效
标题翻译：基板加工方法
公开(公告)号：US07662728B2
公开(公告)日：2010-02-16
申请号：US11431720
申请日：2006-05-11
申请人： Yusaku Kashiwagi , Yasuhiro Oshima , Yoshihisa Kagawa , Gishi Chung
发明人： Yusaku Kashiwagi , Yasuhiro Oshima , Yoshihisa Kagawa , Gishi Chung
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/3121
摘要： A method of forming a low-K dielectric film, comprises the steps of placing a substrate carrying thereon a low-K dielectric film on a stage, heating the low-K dielectric film on the stage, processing the low-K dielectric film by plasma of a processing gas containing a hydrogen gas, the plasma being excited while supplying the processing gas over the low-K dielectric film, wherein the plasma is excited within 90 seconds after placing the substrate upon the stage.
摘要翻译：形成低K电介质膜的方法包括以下步骤：将载有低K电介质膜的衬底放置在载物台上，加热载体上的低K电介质膜，通过等离子体处理低K电介质膜的含有氢气的处理气体，等离子体被激发，同时在低K电介质膜上提供处理气体，其中等离子体在将基板放置在载物台之后的90秒内被激发。

10. 发明申请

US20070131171A1 Plasma process device and plasma process method 有权
标题翻译：等离子体工艺装置和等离子体处理方法
公开(公告)号：US20070131171A1
公开(公告)日：2007-06-14
申请号：US11656379
申请日：2007-01-23
申请人： Koichi Takatsuki , Hikaru Yoshitaka , Shigeo Ashigaki , Yoichi Inoue , Takashi Akahori , Shuuichi Ishizuka , Syoichi Abe , Takashi Suzuki , Kohei Kawamura , Hidenori Miyoshi , Gishi Chung , Yasuhiro Oshima , Hiroyuki Takahashi
发明人： Koichi Takatsuki , Hikaru Yoshitaka , Shigeo Ashigaki , Yoichi Inoue , Takashi Akahori , Shuuichi Ishizuka , Syoichi Abe , Takashi Suzuki , Kohei Kawamura , Hidenori Miyoshi , Gishi Chung , Yasuhiro Oshima , Hiroyuki Takahashi
IPC分类号： C23C16/00
CPC分类号： H01J37/32009 , H01J37/3244 , H01J37/32541
摘要： That surface of an electrode plate 20 which is opposite to a susceptor 10 has a projection shape. The electrode plate 20 is fitted in an opening 26a of shield ring 26 at a projection 20a. At this time, die thickness of the projection 20a is approximately the same as the thickness of the shield ring 26. Accordingly, the electrode plate 20 and the shield ring 26 form substantially the same plane. The major surface of the projection 20a has a diameter 1.2 to 1.5 times the diameter of a wafer W. The electrode plate 20 is formed of, for example, SiC.
摘要翻译：与基座10相对的电极板20的表面具有突起形状。电极板20在突出部20a安装在屏蔽环26的开口26a中。此时，突出部20a的芯片厚度与屏蔽环26的厚度大致相同。因此，电极板20和屏蔽环26形成大致相同的平面。突起部20a的主表面的直径为晶片W的直径的1.2〜1.5倍。电极板20例如由SiC形成。

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