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1. 发明授权

US06207595B1 Laminate and method of manufacture thereof 失效
标题翻译：层压板及其制造方法
公开(公告)号：US06207595B1
公开(公告)日：2001-03-27
申请号：US09033505
申请日：1998-03-02
申请人： Bernd K. Appelt , Lawrence R. Blumberg , William T. Fotorny , Ross D. Havens , Robert M. Japp , Kostas Papathomas , Jan Obrzut , Mark D. Poliks , Amarjit S. Rai
发明人： Bernd K. Appelt , Lawrence R. Blumberg , William T. Fotorny , Ross D. Havens , Robert M. Japp , Kostas Papathomas , Jan Obrzut , Mark D. Poliks , Amarjit S. Rai
IPC分类号： B32B2704
CPC分类号： H01L23/564 , H01L23/08 , H01L23/145 , H01L2924/0002 , H05K1/0366 , H05K2201/029 , H05K2201/0761 , Y10T442/2475 , Y10T442/2959 , Y10T442/2992 , H01L2924/00
摘要： A fabric material and method of its manufacture suitable for use in electronic packages including chip carriers. High insulation resistance is exhibited when subjected to high temperatures and humidity stress conditions.
摘要翻译：一种其制造的织物材料及其制造方法，其适用于包括芯片载体的电子封装。当受到高温和高湿度条件的影响时，表现出高的绝缘电阻。

2. 发明授权

US06555762B2 Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition 有权
标题翻译：电子封装，其具有填充有聚合物和导电组合物的导电通孔的基板
公开(公告)号：US06555762B2
公开(公告)日：2003-04-29
申请号：US09345428
申请日：1999-07-01
申请人： Bernd K. Appelt , Jeffrey D. Gelorme , Sung Kwon Kang , Voya R. Markovich , Kostas Papathomas , Sampath Purushothaman
发明人： Bernd K. Appelt , Jeffrey D. Gelorme , Sung Kwon Kang , Voya R. Markovich , Kostas Papathomas , Sampath Purushothaman
IPC分类号： H05K111
CPC分类号： H01L23/49827 , H01B1/02 , H01B1/22 , H01L23/49866 , H01L2924/0002 , H05K1/095 , H05K3/4069 , Y10T428/12181 , Y10T428/2991 , Y10T428/2993 , Y10T428/2998 , H01L2924/00
摘要： The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.
摘要翻译：本发明提供了一种独特的，高密度的电子封装，其具有用于填充通孔或通孔的导电组合物，以使得从电介质层到相邻电路的可靠的垂直或Z-连接。通孔可以在填充之前进行镀覆或非电镀。还公开了使用该特征制造高密度电子封装的描述。

3. 发明授权

US5194930A Dielectric composition and solder interconnection structure for its use 失效
标题翻译：电介质组成和焊料互连结构供其使用
公开(公告)号：US5194930A
公开(公告)日：1993-03-16
申请号：US760654
申请日：1991-09-16
申请人： Kostas Papathomas , Mark D. Poliks , David W. Wang , Frederick R. Christie
发明人： Kostas Papathomas , Mark D. Poliks , David W. Wang , Frederick R. Christie
IPC分类号： C09J163/00 , H01L21/56 , H01L23/29 , H01L23/31
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01014 , H01L2924/01019 , H01L2924/01087 , H01L2924/10253
摘要： Composition and solder interconnection structure for its use, wherein the gap created by solder connections between a carrier substrate and a semiconductor chip device mounted thereon is filled with the solvent free formulation obtained by curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof, polyol, and filler which is substantially free of alpha particle emissions.
摘要翻译：用于其使用的组合物和焊料互连结构，其中通过在载体衬底和安装在其上的半导体芯片器件之间的焊料连接产生的间隙填充有通过固化含有脂环族聚环氧化物和/或可固化氰酸酯的制剂而获得的无溶剂配方，或其预聚物，多元醇和基本上不含α粒子排放物的填料。

4. 发明申请

US20110284273A1 POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME 有权
标题翻译：在电路基板中使用的电源芯及其制造方法
公开(公告)号：US20110284273A1
公开(公告)日：2011-11-24
申请号：US12782187
申请日：2010-05-18
申请人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
发明人： Robert M. Japp , Kostas Papathomas , John S. Kresge , Timothy Antesberger
IPC分类号： H05K1/09 , H05K1/00 , H01R43/00 , H05K1/11
CPC分类号： H05K3/4641 , H05K3/4617 , H05K2201/068 , Y10T29/49117
摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
摘要翻译：适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。还提供了制造电源芯和电路化基板的方法。使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题。

5. 发明授权

US08198551B2 Power core for use in circuitized substrate and method of making same 有权
标题翻译：用于电路化基板的电源芯及其制造方法
公开(公告)号：US08198551B2
公开(公告)日：2012-06-12
申请号：US12782187
申请日：2010-05-18
申请人： Robert M. Japp , Kostas Papathomas , John Steven Kresge , Timothy Antesberger
发明人： Robert M. Japp , Kostas Papathomas , John Steven Kresge , Timothy Antesberger
IPC分类号： H05K1/11
CPC分类号： H05K3/4641 , H05K3/4617 , H05K2201/068 , Y10T29/49117
摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
摘要翻译：适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。还提供了制造电源芯和电路化基板的方法。使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题。

6. 发明申请

US20080003407A1 Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers 有权
标题翻译：具有介电层的电路化基底，其电介质组成不包括连续或半连续的纤维
公开(公告)号：US20080003407A1
公开(公告)日：2008-01-03
申请号：US11896786
申请日：2007-09-06
申请人： Robert Japp , Kostas Papathomas
发明人： Robert Japp , Kostas Papathomas
IPC分类号： B32B27/06
CPC分类号： H05K1/0373 , H01L2224/16225 , H01L2924/15311 , H05K3/4602 , H05K2201/0209 , H05K2201/0239 , Y10T428/24322 , Y10T428/24355 , Y10T428/24917
摘要： A circuitized substrate which includes at least one circuit layer and at least one substantially solid dielectric layer comprised of a dielectric composition which includes a cured resin material and a predetermined percentage by weight of particulate fillers, but not including continuous or semi-continuous fibers as part thereof.
摘要翻译：一种电路化衬底，其包括至少一个电路层和至少一个基本上固体的电介质层，该电介质层包括固化树脂材料和预定重量百分比的颗粒填料，但不包括连续或半连续纤维作为部分其中。

7. 发明申请

US20060131755A1 Method of making circuitized substrate 有权
标题翻译：制造电路化基板的方法
公开(公告)号：US20060131755A1
公开(公告)日：2006-06-22
申请号：US11349990
申请日：2006-02-09
申请人： Robert Japp , Voya Markovich , Cheryl Palomaki , Kostas Papathomas , David Thomas
发明人： Robert Japp , Voya Markovich , Cheryl Palomaki , Kostas Papathomas , David Thomas
IPC分类号： H01L23/48
CPC分类号： H01L23/145 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H05K1/0373 , H05K3/4602 , H05K2201/0209
摘要： A method of making a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.
摘要翻译：一种制造电路化基板的方法，包括由包括其中包含预定量的颗粒的树脂材料的介电材料构成的第一层，并且不包括连续纤维，半连续纤维等作为其一部分，以及至少一个电路层位于电介质第一层上。

8. 发明授权

US6138350A Process for manufacturing a circuit board with filled holes 失效
标题翻译：用于制造具有填充孔的电路板的工艺
公开(公告)号：US6138350A
公开(公告)日：2000-10-31
申请号：US30587
申请日：1998-02-25
申请人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
发明人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
IPC分类号： H05K1/11 , H05K3/00 , H05K3/02 , H05K3/24 , H05K3/40 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/4652 , H05K1/113 , H05K3/4069 , H05K3/4602 , H01L2224/48091 , H01L2224/73204 , H01L2924/12044 , H05K2201/0347 , H05K2201/0355 , H05K2201/092 , H05K2201/0959 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0554 , H05K3/0023 , H05K3/0094 , H05K3/025 , H05K3/246 , H05K3/429 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , Y10T428/24926 , Y10T428/24942 , Y10T428/249996
摘要： A process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent said dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes is provided.
摘要翻译：一种用于制造电路板的方法，包括提供具有电介质表面的电路化基板，提供包括金属层和可剥离膜的剥离结构，将剥离结构层压到电路化基板上，金属层位于邻近所述电介质表面，形成通过剥离结构在电路化基板中的孔，将包含有机基底的填充材料施加到剥离结构上，将牺牲膜施加到填充材料上，以及向牺牲膜施加足够的热和压力以迫使填充材料进入提供基本上填充孔的孔。

9. 发明授权

US06066889A Methods of selectively filling apertures 失效
公开(公告)号：US06066889A
公开(公告)日：2000-05-23
申请号：US158811
申请日：1998-09-22
申请人： Gerald Walter Jones , Heike Marcello , Kostas Papathomas
发明人： Gerald Walter Jones , Heike Marcello , Kostas Papathomas
IPC分类号： H01L21/48 , H05K3/00 , H01L23/04
CPC分类号： H01L21/486 , H05K3/0094 , H05K2201/0959 , H05K2203/0278 , H05K3/0082
摘要： A novel method of filling apertures in substrates, such as through holes, is provided. The method utilizes a photoimageable film, and comprises the following steps: applying a photoimagable, hole fill film over the apertures; reflowing the hole fill film to flow into the apertures; exposing the hole fill film to actinic radiation, preferably ultraviolet light, through a phototool, which preferably has openings slightly larger than the diameter of the apertures; then at least partially curing the hole fill film; and developing the hole fill film to remove the unexposed hole fill film. An advantage of the present method is that the apertures may be selectively filled. After the apertures are filled, the hole fill film is cured, preferably by baking. Thereafter, the substrate is preferably subjected to further processing steps; for example, nubs of cured hole fill film are preferably removed. If desired, the substrate is circuitized. If desired, features are gold plated, such as for example, electrolessly gold plated. The hole fill film preferably has solids which comprise 0 to about 20% of a thixotrope and about 80% to about 100% parts of an epoxy resin system; the epoxy resin system comprises: from about 10% to about 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to about 130,000; from about 20% to about 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to about 10,000; from about 35% to about 50% of a diglycidyl ether of bisphenol A, preferably halogenated, and having a molecular weight of from about 600 to about 2,500; and from about 0.1 to about 15 parts by weight of the total resin weight, a cationic photoinitiator. The invention also relates to circuitized structures produced according to the method.

10. 发明授权

US08445094B2 Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers 有权
标题翻译：具有介电层的电路化基底，其电介质组成不包括连续或半连续的纤维
公开(公告)号：US08445094B2
公开(公告)日：2013-05-21
申请号：US11896786
申请日：2007-09-06
申请人： Robert Japp , Kostas Papathomas
发明人： Robert Japp , Kostas Papathomas
IPC分类号： B32B3/24 , H05K1/03
CPC分类号： H05K1/0373 , H01L2224/16225 , H01L2924/15311 , H05K3/4602 , H05K2201/0209 , H05K2201/0239 , Y10T428/24322 , Y10T428/24355 , Y10T428/24917
摘要： A circuitized substrate which includes at least one circuit layer and at least one substantially solid dielectric layer comprised of a dielectric composition which includes a cured resin material and a predetermined percentage by weight of particulate fillers, but not including continuous or semi-continuous fibers as part thereof.
摘要翻译：一种电路化衬底，其包括至少一个电路层和至少一个基本上固体的电介质层，该电介质层包括固化树脂材料和预定重量百分比的颗粒填料，但不包括连续或半连续纤维作为部分其中。

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