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1. 发明授权

US5455194A Encapsulation method for localized oxidation of silicon with trench isolation 失效
标题翻译：具有沟槽隔离的硅的局部氧化的封装方法
公开(公告)号：US5455194A
公开(公告)日：1995-10-03
申请号：US398844
申请日：1995-03-06
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76227 , Y10S148/05
摘要： A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).
摘要翻译：用于制造沟槽隔离区（44）的方法包括沉积第一，第二和第三可氧化层（28,34,42）。沉积第一可氧化层（28）以覆盖形成在半导体衬底（10）中的沟槽（12）的表面。第一可氧化层（28）还填充形成在掩模层（14）中的凹部（26），并且邻近沟槽（12）的上表面驻留。在氧化第一可氧化层（28）之后，沉积第二可氧化层（34）以填充沟槽（12）。沉积第三可氧化层（42）以覆盖第二可氧化层（34）并填充凹部（26）的剩余部分。进行氧化处理以氧化可氧化层（42）和一部分第二可氧化层（34）以形成沟槽隔离区（44）。在本发明的替代实施例中，在隔离区（44）附近形成浅隔离区（46）。

2. 再颁专利

USRE35294E Polysilicon encapsulated localized oxidation of silicon 失效
标题翻译：多晶硅封装了硅的局部氧化
公开(公告)号：USRE35294E
公开(公告)日：1996-07-09
申请号：US245131
申请日：1994-05-17
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32 , Y10S148/117
摘要： A reduction in defects and lateral encroachment is obtained by .[.utilizing a high pressure oxidation in conjunction with.]. an oxidizable layer conformally deposited over an oxidation mask. .[.The.]. .Iadd.In one embodiment, the .Iaddend.use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited..Iadd.Alternately, lateral encroachment can be controlled by intentionally growing an oxide layer on the substrate surface. .Iaddend.
摘要翻译：缺陷和横向侵蚀的减少通过[利用高压氧化与]氧化掩膜上共形沉积的可氧化层来获得。在一个实施方案中，使用高压氧化提供形成LOCOS氧化物而不形成缺陷。存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。在本实施例中，可以除去可充当氧扩散管的任何氧化物。因此，表现为名义上或没有横向侵占。或者，可以通过在衬底表面上有意地生长氧化物层来控制横向侵蚀。

3. 发明授权

US5175123A High-pressure polysilicon encapsulated localized oxidation of silicon 失效
标题翻译：高压多晶硅封装了硅的局部氧化
公开(公告)号：US5175123A
公开(公告)日：1992-12-29
申请号：US612174
申请日：1990-11-13
申请人： Barbara Vasquez , Michael P. Masquelier
发明人： Barbara Vasquez , Michael P. Masquelier
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/32 , Y10S148/117
摘要： A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.
摘要翻译：通过利用高压氧化与保形地沉积在氧化掩模上的可氧化层结合来获得缺陷和横向侵蚀的减少。使用高压氧化提供形成LOCOS氧化物而不形成缺陷。存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。在本实施例中，可以除去可充当氧扩散管的任何氧化物。因此，表现为名义上或没有横向侵占。

4. 发明申请

US20070229102A1 MECHANICALLY RECONFIGURABLE VERTICAL TESTER INTERFACE FOR IC PROBING 有权
标题翻译：用于IC探测的机械可重构的垂直测试仪接口
公开(公告)号：US20070229102A1
公开(公告)日：2007-10-04
申请号：US11761912
申请日：2007-06-12
申请人： Benjamin Eldridge , Barbara Vasquez , Makarand Shinde , Gaetan Mathieu , A. Sporck
发明人： Benjamin Eldridge , Barbara Vasquez , Makarand Shinde , Gaetan Mathieu , A. Sporck
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/0416 , G01R1/07307
摘要： A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, or pluggable and unpluggable enabling movement over a range of positions.
摘要翻译：晶片测试组件包括多个探针头基底，其布置成瓦片，其中连接器连接到一侧，探针支撑在相对侧上。在一个实施例中，柔性电缆连接器将探头头瓦片上的连接器直接连接到测试头，而在另一个实施例中，柔性电缆将探头头瓦片连接到PCB，从而向测试头连接器提供水平布线。在一个实施例中，调平销提供连接到附接到瓦片的保持元件以提供施加推挽平整力的简化支撑结构。测试头连接器接口框架能够重新布置测试头和探针卡之间的连接器，以提供完整的晶片接触或部分晶片接触。测试头连接器通过在轨道上滑动来重新布置，或者可插拔和可拔出，使得能够在一定范围的位置上移动。

5. 发明申请

US20050277323A1 Mechanically reconfigurable vertical tester interface for IC probing 失效
标题翻译：用于IC探测的机械可重构垂直测试仪接口
公开(公告)号：US20050277323A1
公开(公告)日：2005-12-15
申请号：US10868425
申请日：2004-06-15
申请人： Benjamin Eldridge , Barbara Vasquez , Makarand Shinde , Gaetan Mathieu , A. Sporck
发明人： Benjamin Eldridge , Barbara Vasquez , Makarand Shinde , Gaetan Mathieu , A. Sporck
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28 , H01R11/18
CPC分类号： G01R31/2889 , G01R1/0416 , G01R1/07307
摘要： A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, or pluggable and unpluggable enabling movement over a range of positions.
摘要翻译：晶片测试组件包括多个探针头基底，其布置成瓦片，其中连接器连接到一侧，探针支撑在相对侧上。在一个实施例中，柔性电缆连接器将探头头瓦片上的连接器直接连接到测试头，而在另一个实施例中，柔性电缆将探头头瓦片连接到PCB，从而向测试头连接器提供水平布线。在一个实施例中，调平销提供连接到附接到瓦片的保持元件以提供施加推挽平整力的简化支撑结构。测试头连接器接口框架能够重新布置测试头和探针卡之间的连接器，以提供完整的晶片接触或部分晶片接触。测试头连接器通过在轨道上滑动来重新布置，或者可插拔和可拔出，使得能够在一定范围的位置上移动。

6. 发明授权

US06916185B2 Connection of integrated circuit to a substrate 失效
标题翻译：将集成电路连接到基板
公开(公告)号：US06916185B2
公开(公告)日：2005-07-12
申请号：US10464429
申请日：2003-06-18
申请人： Harry Hedler , Barbara Vasquez
发明人： Harry Hedler , Barbara Vasquez
IPC分类号： H01L23/48 , H01L21/60 , H05K3/34 , H01R12/00 , H05K1/00
CPC分类号： H01L24/81 , H01L24/14 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/1403 , H01L2224/14051 , H01L2224/14505 , H01L2224/16106 , H01L2224/17517 , H01L2224/81136 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01072 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by performing the steps of: providing a main area (HF1) of the integrated circuit (1), which has an electrical contacting region (2), with a mechanical supporting structure (3a, 3b; 33a, 33b, 33c; 43a, 43b, 43c); providing a solderable surface region (5a, 5b; 35a, 35b, 35c; 60a, 60b, 60c) of the mechanical supporting structure (3a, 3b; 33a, 33b, 33c; 43a, 43b, 43c); providing a solderable terminal region (10; 5, 30; 40, 50), which is electrically connected to the electrical contacting region (2), on the main area (HF1) of the integrated circuit (1); providing a main area (HF2) of the substrate (20) with a first soldering region (22′, 23′; 22′, 23′, 22″, 23″), which can be aligned with the solderable surface regions (5a, 5b; 35a, 35b, 35c; 60a, 60b, 60c), and with a second soldering region (22, 23), which can be aligned with the solderable terminal region (10; 5, 30; 40, 50); and simultaneous soldering of the surface regions (5a, 5b; 35a, 35b, 35c; 60a, 60b, 60c) to the first soldering region (22′, 23′; 22′, 23′, 22″, 23″) and of the terminal region (10; 5, 30; 40, 50) to the second soldering region (22, 23).
摘要翻译：本发明提供了一种将集成电路连接到基板和相应的电路装置的方法。通过执行以下步骤进行连接：提供具有电接触区域（2）的集成电路（1）的主区域（HF 1），其具有机械支撑结构（3a，3b; 33a，33b b，33c; 43a，43b，43c）; 提供机械支撑结构（3a，3b; 33a，33b，33c）的可焊接表面区域（5a，5b; 35a，35b，35c; 60a，60b，60c） ; 43 a，43 b，43 c）; 在所述集成电路（1）的主区域（HF 1）上提供与所述电接触区域（2）电连接的可焊接终端区域（10; 5,30; 40,50）通过第一焊接区域（22'，23'; 22'，23'，22“，23”）提供基板（20）的主区域（HF 2），其可与可焊接表面区域（5a，5b; 35a，35b，35c; 60a，60b，60c）以及可与可焊接终端区域（10; ...）对齐的第二焊接区域（22,23） 5，30; 40，50）; 以及将所述表面区域（5a，5b; 35a，35b，35c; 60a，60b，60c）同时焊接到所述第一焊接区域（22'，23'; 22'，23' 22“，23”）和端子区域（10; 5,30; 40,50）连接到第二焊接区域（22,23）。

7. 发明授权

US06714418B2 Method for producing an electronic component having a plurality of chips that are stacked one above the other and contact-connected to one another 有权
标题翻译：一种电子部件的制造方法，所述电子部件具有多个堆叠在一起并且彼此接触连接的芯片
公开(公告)号：US06714418B2
公开(公告)日：2004-03-30
申请号：US10285924
申请日：2002-11-01
申请人： Gerd Frankowsky , Harry Hedler , Roland Irsigler , Thorsten Meyer , Barbara Vasquez
发明人： Gerd Frankowsky , Harry Hedler , Roland Irsigler , Thorsten Meyer , Barbara Vasquez
IPC分类号： H05K702
CPC分类号： H01L25/50 , H01L21/568 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L2224/04105 , H01L2224/05548 , H01L2224/05573 , H01L2224/12105 , H01L2224/16145 , H01L2224/16237 , H01L2224/17181 , H01L2224/32225 , H01L2224/73267 , H01L2225/1035 , H01L2225/1064 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/15331 , H01L2924/00
摘要： An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection. Subsequently, each of the components, which comprise a stack of chips, is separated from the assembled stack of chip arrangements.
摘要翻译：电子部件具有多个彼此叠置并彼此接触连接的芯片。为了形成该部件，第一平面芯片布置设置有功能芯片，其格栅彼此间隔开，并且在芯片之间的空间中具有填充材料，以形成固定芯片的绝缘保持框架，框架具有芯片用于与另一个芯片布置的另一芯片的电接触连接的每个芯片具有专用的导电条。通过与第一平面芯片布置相同的方法形成至少一个附加的平面芯片布置，然后将其堆叠在第一平面芯片布置上，使得两个芯片布置在另一个之上并且两个相应的触点连接元件芯片布置彼此连接以进行电芯片到芯片的接触连接。随后，包括一堆芯片的每个部件与组装的芯片布置堆叠分离。

8. 发明授权

US5773986A Semiconductor wafer contact system and method for contacting a semiconductor wafer 失效
标题翻译：用于接触半导体晶片的半导体晶片接触系统和方法
公开(公告)号：US5773986A
公开(公告)日：1998-06-30
申请号：US416121
申请日：1995-04-03
申请人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
发明人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
IPC分类号： G01R31/28 , G01R1/073
CPC分类号： G01R31/2886 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078
摘要： A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).
摘要翻译：半导体晶片接触系统包括含有不可压缩材料的密封囊（32）。密封的囊（32）压靠包括电触头阵列（30）的柔性电路层（28）。气囊（32）迫使电触点阵列抵靠在半导体晶片（10）的芯片（11）上的相应阵列的器件电触点（12）。囊（32）的形状适应于补偿接触高度和非平行度下的晶片级和晶片级不规则性。另外，囊（32）确保膜接触件（30）和管芯接触件（12）之间跨越整个晶片（10）的恒定的力。

9. 发明授权

US5004703A Multiple trench semiconductor structure method 失效
标题翻译：多沟槽半导体结构方法
公开(公告)号：US5004703A
公开(公告)日：1991-04-02
申请号：US382947
申请日：1989-07-21
申请人： Peter J. Zdebel , Barbara Vasquez
发明人： Peter J. Zdebel , Barbara Vasquez
IPC分类号： H01L21/308
CPC分类号： H01L21/3085 , H01L21/3081
摘要： A method of fabricating multiple trench semiconductor structures wherein a preferred embodiment includes forming an epitaxial silicon layer on a silicon substrate and a dielectric layer on the epitaxial silicon layer. An opening is then formed which extends through the dielectric layer and into the epitaxial silicon layer. Sidewall spacers are formed in the opening and an oxide lens is formed in the opening between the sidewall spacers. The sidewall spacers are then removed and trenches are formed in the opening where the sidewall spacers were formerly disposed.
摘要翻译：一种制造多个沟槽半导体结构的方法，其中优选实施例包括在硅衬底上形成外延硅层和外延硅层上的电介质层。然后形成延伸穿过介电层并进入外延硅层的开口。侧壁间隔件形成在开口中，并且氧化物透镜形成在侧壁间隔件之间的开口中。然后去除侧壁间隔物，并且在先前设置侧壁间隔物的开口中形成沟槽。

10. 发明授权

US07659736B2 Mechanically reconfigurable vertical tester interface for IC probing 有权
标题翻译：用于IC探测的机械可重构垂直测试仪接口
公开(公告)号：US07659736B2
公开(公告)日：2010-02-09
申请号：US11761912
申请日：2007-06-12
申请人： Benjamin N. Eldridge , Barbara Vasquez , Makarand S. Shinde , Gaetan L. Mathieu , A. Nicholas Sporck
发明人： Benjamin N. Eldridge , Barbara Vasquez , Makarand S. Shinde , Gaetan L. Mathieu , A. Nicholas Sporck
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/0416 , G01R1/07307
摘要： A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, or pluggable and unpluggable enabling movement over a range of positions.
摘要翻译：晶片测试组件包括多个探针头基底，其布置成瓦片，其中连接器连接到一侧，探针支撑在相对侧上。在一个实施例中，柔性电缆连接器将探头头瓦片上的连接器直接连接到测试头，而在另一个实施例中，柔性电缆将探头头瓦片连接到PCB，从而向测试头连接器提供水平布线。在一个实施例中，调平销提供连接到附接到瓦片的保持元件以提供施加推挽平整力的简化支撑结构。测试头连接器接口框架能够重新布置测试头和探针卡之间的连接器，以提供完整的晶片接触或部分晶片接触。测试头连接器通过在轨道上滑动来重新布置，或者可插拔和可拔出，使得能够在一定范围的位置上移动。

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