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1. 再颁专利

USRE35294E Polysilicon encapsulated localized oxidation of silicon 失效
标题翻译：多晶硅封装了硅的局部氧化
公开(公告)号：USRE35294E
公开(公告)日：1996-07-09
申请号：US245131
申请日：1994-05-17
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32 , Y10S148/117
摘要： A reduction in defects and lateral encroachment is obtained by .[.utilizing a high pressure oxidation in conjunction with.]. an oxidizable layer conformally deposited over an oxidation mask. .[.The.]. .Iadd.In one embodiment, the .Iaddend.use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited..Iadd.Alternately, lateral encroachment can be controlled by intentionally growing an oxide layer on the substrate surface. .Iaddend.
摘要翻译：缺陷和横向侵蚀的减少通过[利用高压氧化与]氧化掩膜上共形沉积的可氧化层来获得。在一个实施方案中，使用高压氧化提供形成LOCOS氧化物而不形成缺陷。存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。在本实施例中，可以除去可充当氧扩散管的任何氧化物。因此，表现为名义上或没有横向侵占。或者，可以通过在衬底表面上有意地生长氧化物层来控制横向侵蚀。

2. 发明授权

US5455194A Encapsulation method for localized oxidation of silicon with trench isolation 失效
标题翻译：具有沟槽隔离的硅的局部氧化的封装方法
公开(公告)号：US5455194A
公开(公告)日：1995-10-03
申请号：US398844
申请日：1995-03-06
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76227 , Y10S148/05
摘要： A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).
摘要翻译：用于制造沟槽隔离区（44）的方法包括沉积第一，第二和第三可氧化层（28,34,42）。沉积第一可氧化层（28）以覆盖形成在半导体衬底（10）中的沟槽（12）的表面。第一可氧化层（28）还填充形成在掩模层（14）中的凹部（26），并且邻近沟槽（12）的上表面驻留。在氧化第一可氧化层（28）之后，沉积第二可氧化层（34）以填充沟槽（12）。沉积第三可氧化层（42）以覆盖第二可氧化层（34）并填充凹部（26）的剩余部分。进行氧化处理以氧化可氧化层（42）和一部分第二可氧化层（34）以形成沟槽隔离区（44）。在本发明的替代实施例中，在隔离区（44）附近形成浅隔离区（46）。

3. 发明授权

US5175123A High-pressure polysilicon encapsulated localized oxidation of silicon 失效
标题翻译：高压多晶硅封装了硅的局部氧化
公开(公告)号：US5175123A
公开(公告)日：1992-12-29
申请号：US612174
申请日：1990-11-13
申请人： Barbara Vasquez , Michael P. Masquelier
发明人： Barbara Vasquez , Michael P. Masquelier
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/32 , Y10S148/117
摘要： A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.
摘要翻译：通过利用高压氧化与保形地沉积在氧化掩模上的可氧化层结合来获得缺陷和横向侵蚀的减少。使用高压氧化提供形成LOCOS氧化物而不形成缺陷。存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。在本实施例中，可以除去可充当氧扩散管的任何氧化物。因此，表现为名义上或没有横向侵占。

4. 发明授权

US4966858A Method of fabricating a lateral semiconductor structure including field plates for self-alignment 失效
标题翻译：制造包括用于自对准的场板的横向半导体结构的方法
公开(公告)号：US4966858A
公开(公告)日：1990-10-30
申请号：US430396
申请日：1989-11-02
申请人： Michael P. Masquelier , David N. Okada
发明人： Michael P. Masquelier , David N. Okada
IPC分类号： H01L21/60 , H01L29/06 , H01L29/40 , H01L29/735 , H01L29/78
CPC分类号： H01L29/402 , H01L21/76897 , H01L29/735 , H01L29/7813 , Y10S148/013 , Y10S148/045 , Y10S148/167
摘要： A method of fabricating a lateral semiconductor structure includes providing a semiconductor substrate and forming wells therein. Following formation of a dielectric layer on the substrate, field region openings are formed through which field regions are implanted into the substrate. The self-aligned formation of field oxidation regions to the field region openings then occurs and is followed by the formation of field plates on the field oxidation regions. A first active device region is then formed in said substrate, the formation of which is self-aligned to the field plates. This is followed by the formation of a second active device region in the first active device region which is also self-aligned to the field plates. The resulting structure allows for high speed devices that maintain consistently high current gain without sacrificing Early or breakdown voltages.
摘要翻译：制造横向半导体结构的方法包括提供半导体衬底并在其中形成阱。在衬底上形成电介质层之后，形成场区开口，通过该场区开口将场区注入到衬底中。然后发生场氧化区域到场区开口的自对准形成，随后在场氧化区域上形成场板。然后在所述衬底中形成第一有源器件区，其形成与场板自对准。接下来是在第一有源器件区域中形成第二有源器件区域，该第二有源器件区域也与场板自对准。所得到的结构允许高速器件保持恒定的高电流增益而不牺牲早期或击穿电压。

5. 发明授权

US5482878A Method for fabricating insulated gate field effect transistor having subthreshold swing 失效
标题翻译：具有亚阈值摆幅的绝缘栅场效应晶体管的制造方法
公开(公告)号：US5482878A
公开(公告)日：1996-01-09
申请号：US223393
申请日：1994-04-04
申请人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
发明人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/265
CPC分类号： H01L27/0928 , H01L21/823807 , H01L29/7835
摘要： Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.
摘要翻译：绝缘栅场效应晶体管（10,70）具有用于设置VT和器件漏电流的工艺步骤，所述工艺步骤与用于提供穿透保护的工艺步骤分离，从而降低亚阈值摆幅。在单侧晶体管（10）中，源极区（48,51）和漏极区（49,52）之间的掺杂剂层（25,30）的部分（37,45）用作沟道区域，并将 VT和器件漏电流。光晕区域（34,39）包含源极区域（48,51）并设置穿透电压。在双向晶体管（70）中，源极区域（83,86）和漏极区域（84,87）都包含在光晕区域（75,74,79,81）内。掺杂剂层（25,30）的一部分（76,82）设定VT和漏电流，而光晕区域（75,79）设定穿透电压。

6. 发明授权

US07283806B2 Wireless sensing system and method 有权
标题翻译：无线传感系统及方法
公开(公告)号：US07283806B2
公开(公告)日：2007-10-16
申请号：US11114993
申请日：2005-04-25
申请人： Michael P. Masquelier
发明人： Michael P. Masquelier
IPC分类号： H04M1/663 , H04M1/725 , H04Q7/22
CPC分类号： G01D21/00 , G01M5/00
摘要： An apparatus and method is provided for sensing data relating to a structure (14), including an inspection site sensor system having at least one microprocessor (16) coupled to the structure. At least one sensor (12) for sensing data is connected to each of the at least one microprocessors that compare the data to a standard. A user interface (18) is coupled to the microprocessor (16) for presenting the comparison, and a wireless transmitter (20) is coupled to the microprocessor (16) for transmitting at least one of the data and the comparison to a management site (22). The management site (22) includes a receiver (24) for receiving the transmitted at least one of the data and the comparison, a microprocessor (26) coupled to the receiver (24); and a user interface (28) coupled to the microprocessor (26).
摘要翻译：提供了一种用于感测与结构（14）有关的数据的装置和方法，包括具有耦合到该结构的至少一个微处理器（16）的检查位置传感器系统。用于感测数据的至少一个传感器（12）连接到将数据与标准进行比较的至少一个微处理器中的每一个。用户界面（18）耦合到微处理器（16）以呈现比较，并且无线发射器（20）耦合到微处理器（16），用于将数据和比较中的至少一个传送到管理站点 22）。管理站点（22）包括用于接收所发送的数据和比较中的至少一个的接收器（24），耦合到接收器（24）的微处理器（26）; 以及耦合到微处理器（26）的用户接口（28）。

7. 发明授权

US5130262A Internal current limit and overvoltage protection method 失效
标题翻译：内部电流限制和过压保护方法
公开(公告)号：US5130262A
公开(公告)日：1992-07-14
申请号：US704683
申请日：1991-05-17
申请人： Michael P. Masquelier , David N. Okada
发明人： Michael P. Masquelier , David N. Okada
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/36 , H01L29/66 , H01L29/732 , H01L29/735
CPC分类号： H01L29/1004 , H01L29/1008 , H01L29/36 , H01L29/7322 , H01L29/735 , Y10S148/011
摘要： A method of internally limiting current and providing overvoltage protection in a semiconductor device comprises providing a semiconductor device having at least a first junction wherein both sides of the junction have predetermined dopant concentrations and wherein the first junction is spaced apart a predetermined distance from either a second junction or current blocking means. The predetermined dopant concentrations and distance are such that when a predetermined voltage is applied to the device, a depletion region from the first junction encounters either a depletion region from the second junction or current blocking means, thereby pinching off current at a desired voltage. The pinch-off voltage may be varied by adjusting the distance between the first junction and either the second junction or current blocking means and also by adjusting the predetermined dopant concentrations.

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