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1. 发明授权

US08339449B2 Defect monitoring in semiconductor device fabrication 有权
标题翻译：半导体器件制造中的缺陷监测
公开(公告)号：US08339449B2
公开(公告)日：2012-12-25
申请号：US12537269
申请日：2009-08-07
申请人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
发明人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
IPC分类号： H04N7/18
CPC分类号： G06T7/0006 , G01N21/9501 , G06T2207/10061 , G06T2207/30148
摘要： A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.
摘要翻译：提出了一种形成装置的方法。该方法包括提供在其上至少包含部分形成的器件的衬底。该装置包括至少一个缺陷部位。获取缺陷部位的像素化图像，并且每个像素包括灰度值（GLV）。消除了缺陷部位的周围噪声。图像的一个点被识别为缺陷的中心。执行多个迭代以排除围绕缺陷图像的中心的外边缘像素。该缺陷被归类为杀伤或非杀伤性缺陷。

2. 发明授权

US08289508B2 Defect detection recipe definition 有权
标题翻译：缺陷检测配方定义
公开(公告)号：US08289508B2
公开(公告)日：2012-10-16
申请号：US12621510
申请日：2009-11-19
申请人： Victor Seng Keong Lim , Rachel Yie Fang Wai , Fang Hong Gn , Liang Choo Hsia
发明人： Victor Seng Keong Lim , Rachel Yie Fang Wai , Fang Hong Gn , Liang Choo Hsia
IPC分类号： G01N21/00
CPC分类号： H01L22/12
摘要： A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.
摘要翻译：公开了一种形成装置的方法。该方法包括提供衬底并在衬底上处理器件的一层。该层用检查工具检查缺陷。检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。

3. 发明授权

US08178368B2 Test chiplets for devices 有权
标题翻译：测试小巧的设备
公开(公告)号：US08178368B2
公开(公告)日：2012-05-15
申请号：US12621513
申请日：2009-11-19
申请人： Victor Seng Keong Lim , Rachel Yie Fang Wai , Fang Hong Gn , Liang Choo Hsia
发明人： Victor Seng Keong Lim , Rachel Yie Fang Wai , Fang Hong Gn , Liang Choo Hsia
IPC分类号： G06F17/50
CPC分类号： H01L22/12
摘要： A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection.
摘要翻译：公开了一种形成装置的方法。该方法包括提供其上形成有该器件的衬底。它还包括在衬底上形成测试电池。测试单元包括编程到单元中以便于缺陷检测的缺陷。

4. 发明授权

US06403484B1 Method to achieve STI planarization 失效
标题翻译：实现STI平坦化的方法
公开(公告)号：US06403484B1
公开(公告)日：2002-06-11
申请号：US09803187
申请日：2001-03-12
申请人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
发明人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76229
摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法。通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。去除覆盖在第一蚀刻停止层上的暴露的氧化物层。去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

5. 发明授权

US07060573B2 Extended poly buffer STI scheme 失效
公开(公告)号：US07060573B2
公开(公告)日：2006-06-13
申请号：US09759909
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
IPC分类号： H01L21/336
CPC分类号： H01L21/76232
摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

6. 发明授权

US06815823B2 Copper metal structure for the reduction of intra-metal capacitance 失效
标题翻译：铜金属结构用于降低金属间电容
公开(公告)号：US06815823B2
公开(公告)日：2004-11-09
申请号：US10679736
申请日：2003-10-06
申请人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
发明人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31138 , H01L21/76804 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
摘要翻译：提供了一种新的方法和结构来创建互连线。在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

7. 发明授权

US07939348B2 E-beam inspection structure for leakage analysis 有权
标题翻译：用于泄漏分析的电子束检查结构
公开(公告)号：US07939348B2
公开(公告)日：2011-05-10
申请号：US11845787
申请日：2007-08-28
申请人： Victor Seng Keong Lim , Jeffrey Lam
发明人： Victor Seng Keong Lim , Jeffrey Lam
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , G01R31/2884 , G01R31/307
摘要： A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.
摘要翻译：测试结构和使用测试结构的方法，其中测试结构由八个测试结构中的至少一个组成，当电压对比度扫描具有至少一个预定的结构缺陷时，其具有可辨别的缺陷特征。八个测试结构为：1）具有有源面积（AA）/ P-N结泄漏; 2）具有对地的隔离区域; 3）具有AA / P-N结和隔离区; 4）具有栅极电介质泄漏和栅极到隔离区域对地; 5）具有通过AA / P-N结到漏电的栅极电介质泄漏; 6）具有栅极电介质接地和栅极/一侧隔离区域泄漏到地面; 7）具有通过AA / P-N结到接地漏电的超大栅极电介质; 和8）具有AA / P-N结泄漏栅介质泄漏。

8. 发明授权

US06649517B2 Copper metal structure for the reduction of intra-metal capacitance 有权
标题翻译：铜金属结构用于降低金属间电容
公开(公告)号：US06649517B2
公开(公告)日：2003-11-18
申请号：US09859353
申请日：2001-05-18
申请人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
发明人： Young-Way Teh , Victor Seng Keong Lim , Ting Cheong Ang
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/31138 , H01L21/76804 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
摘要翻译：提供了一种新的方法和结构来创建互连线。在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

9. 发明授权

US06406975B1 Method for fabricating an air gap shallow trench isolation (STI) structure 失效
标题翻译：制造气隙浅沟槽隔离（STI）结构的方法
公开(公告)号：US06406975B1
公开(公告)日：2002-06-18
申请号：US09721718
申请日：2000-11-27
申请人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
发明人： Victor Seng Keong Lim , Young-Way Teh , Ting-Cheong Ang , Alex See , Yong Kong Siew
IPC分类号： H01L2176
CPC分类号： H01L21/764 , H01L21/76232
摘要： A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
摘要翻译：制造具有气隙的浅沟槽隔离（STI）的方法，该气隙是通过将有机填充材料分解成盖层形成的。衬底层和阻挡层形成在衬底上。衬垫层和阻挡层被图案化以形成沟槽开口。我们通过蚀刻通过沟槽开口在衬底中形成沟槽。第一衬里层形成在沟槽的侧壁上。在阻挡层和第一衬里层上的第二衬里层。在第二衬垫层上形成填充材料以填充沟槽。在重要的步骤中，覆盖层沉积在填充材料和第二衬里层上。对填充材料进行等离子体处理并加热以使填充材料汽化，使得填充材料通过盖层扩散以形成间隙。绝缘层沉积在覆盖层上。绝缘层被平坦化。去除阻挡层。

10. 发明授权

US06376376B1 Method to prevent CU dishing during damascene formation 有权
标题翻译：防止大马士革形成期间CU凹陷的方法
公开(公告)号：US06376376B1
公开(公告)日：2002-04-23
申请号：US09760165
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Wang Ling Goh
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.
摘要翻译：描述了利用在氮化物和阻挡层之间的附加氧化物层的铜镶嵌金属化的新方法，以防止CMP之后的铜线的凹陷。提供了覆盖半导体衬底中的半导体器件结构的绝缘层。覆盖在绝缘层上的抛光阻挡层被沉积。沉积在抛光停止层上的氧化物层。通过氧化物层，抛光停止层和绝缘层将开口蚀刻到半导体器件结构之一。在氧化物层的表面和开口内沉积阻挡金属层。在阻挡金属层的表面上沉积铜层。铜层和不在开口内的阻挡金属层被抛光，其中阻挡金属层比铜层抛光得更慢，从而发生铜层的凹陷。此后，在抛光停止层处停止氧化物层，其中氧化物层比铜层更快地抛光，由此去除铜层的凹陷，并且在氧化物层完全在铜层上形成隆起抛光在制造集成电路时，铜层被过度抛光以去除凸起以完成铜镶嵌金属化。

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