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1. 发明授权

US07060573B2 Extended poly buffer STI scheme 失效
公开(公告)号：US07060573B2
公开(公告)日：2006-06-13
申请号：US09759909
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
IPC分类号： H01L21/336
CPC分类号： H01L21/76232
摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

2. 发明授权

US06403484B1 Method to achieve STI planarization 失效
标题翻译：实现STI平坦化的方法
公开(公告)号：US06403484B1
公开(公告)日：2002-06-11
申请号：US09803187
申请日：2001-03-12
申请人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
发明人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76229
摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法。通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。去除覆盖在第一蚀刻停止层上的暴露的氧化物层。去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

3. 发明授权

US06204137B1 Method to form transistors and local interconnects using a silicon nitride dummy gate technique 有权
标题翻译：使用氮化硅虚拟栅极技术形成晶体管和局部互连的方法
公开(公告)号：US06204137B1
公开(公告)日：2001-03-20
申请号：US09556386
申请日：2000-04-24
申请人： Kok Hin Teo , Feng Chen , Alex See , Lap Chan
发明人： Kok Hin Teo , Feng Chen , Alex See , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/76224
摘要： A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.
摘要翻译：已经实现了形成MOS晶体管的新方法。生长衬垫氧化物层。沉积氮化硅层。沟槽蚀刻为计划的STI。在沟槽内生长沟槽衬垫。沉积填充沟槽的沟槽氧化物层。将沟槽氧化物层抛光以完成STI。将相同的氮化硅层图案化以形成伪栅极。沉积栅极衬垫层。植入离子以形成轻掺杂的漏极结。侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。植入离子以形成漏极和源极结。生长在源极和漏极结上方的外延硅层。沉积金属层。将外延硅层转化为硅化物以形成硅化源极和漏极触点。将层间电介质层沉积并抛光到虚拟栅极。蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。在晶体管栅极开口上沉积栅极氧化物层。沉积栅极电极层以填充晶体管栅极开口。图案化栅极电极层以完成晶体管栅极。

4. 发明授权

US6103569A Method for planarizing local interconnects 有权
标题翻译：平面化局部互连的方法
公开(公告)号：US6103569A
公开(公告)日：2000-08-15
申请号：US459730
申请日：1999-12-13
申请人： Kok Hin Teo , Feng Chen , Lap Chan
发明人： Kok Hin Teo , Feng Chen , Lap Chan
IPC分类号： H01L21/321 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76895
摘要： A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.
摘要翻译：用于平面化用于器件互连的金属插头的方法。该过程开始于在其上提供至少一个装置的半导体结构。在器件和半导体结构上形成介电层。在介电层上形成第一阻挡金属层，在第一阻挡金属层上形成牺牲氧化物层。牺牲氧化物层，第一阻挡金属层和电介质层被图案化以形成接触开口。在半导体结构上形成第二阻挡金属层，在第二阻挡金属层上形成金属接触层。使用第一化学机械抛光工艺对金属接触层和第二阻挡金属层进行平面化处理，并去除牺牲氧化物层。使用第二化学机械抛光工艺将金属接触层和第一阻挡金属层平坦化。

5. 发明授权

US06274485B1 Method to reduce dishing in metal chemical-mechanical polishing 失效
标题翻译：减少金属化学机械抛光中的凹陷的方法
公开(公告)号：US06274485B1
公开(公告)日：2001-08-14
申请号：US09425310
申请日：1999-10-25
申请人： Feng Chen , Rick Teo , Lap Chan
发明人： Feng Chen , Rick Teo , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is described. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received. Since the metal polishing rate is higher than the oxide polishing rate, the convex shape is made substantially planar during the over-polishing to complete metal plug metallization in the fabrication of an integrated circuit.
摘要翻译：描述了利用牺牲高抛光速率层以防止CMP之后的凹陷和金属残余物的金属插塞金属化的新方法。半导体衬底上半导体器件结构上覆盖氧化物层。牺牲高抛光速率（HPR）层沉积在氧化物层上。通过HPR层和氧化物层将开口蚀刻到半导体器件结构之一。阻挡层和金属层沉积在HPR层的表面上并且在开口内。覆盖氧化物层的金属层，阻挡层和HPR层通过CMP抛光。 HPR层的抛光速率高于金属层的抛光速率，结果是在HPR层被完全去除之后，残留在开口内的金属层具有凸形状。氧化层被过度抛光，直到接收端点检测。由于金属抛光速率高于氧化物研磨速度，因此在制造集成电路时，在抛光过程中使凸形形状基本上平坦，以完成金属插塞金属化。

6. 发明授权

US09262732B2 System and method of enterprise action item planning, executing, tracking and analytics 有权
标题翻译：企业行动项目计划，执行，跟踪和分析的系统和方法
公开(公告)号：US09262732B2
公开(公告)日：2016-02-16
申请号：US13166501
申请日：2011-06-22
申请人： Bin Duan , Lap Chan
发明人： Bin Duan , Lap Chan
IPC分类号： G06Q10/06 , H04W64/00
CPC分类号： G06Q10/0631 , H04W64/006
摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
摘要翻译：跟踪企业数据处理环境中的动作项目的系统和方法。该方法包括由客户端从服务器接收包括位置的动作项目。该方法还包括由客户端在与该动作项目相关的位置处执行登记。该方法还包括由客户端执行与该动作项目相关的退房。该方法还包括由客户端改变动作项目的状态。以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

7. 发明申请

US20140123068A1 Content Management Systems and Methods 有权
标题翻译：内容管理系统与方法
公开(公告)号：US20140123068A1
公开(公告)日：2014-05-01
申请号：US13661687
申请日：2012-10-26
申请人： Lap Chan
发明人： Lap Chan
IPC分类号： G06F3/048
CPC分类号： G06F3/04817 , G06F3/0482 , G06F3/0486 , G06F3/04886 , H04M1/72519
摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.
摘要翻译：描述了管理内容的示例系统和方法。在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

8. 发明授权

US07932152B2 Method of forming a gate stack structure 有权
标题翻译：形成栅极堆叠结构的方法
公开(公告)号：US07932152B2
公开(公告)日：2011-04-26
申请号：US12025789
申请日：2008-02-05
申请人： Will Wong , Lap Chan , Alan Lek
发明人： Will Wong , Lap Chan , Alan Lek
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.
摘要翻译：一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。在衬底上形成第一厚度的第一材料的第一层。第一层的一部分在主区域上被去除以暴露衬底。该结构暴露于氧化介质。这形成例如基板的氧化物材料主区域的第二层。第二层具有第二厚度。另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。第三层具有第三厚度。

9. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

10. 发明申请

US20050156269A1 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US20050156269A1
公开(公告)日：2005-07-21
申请号：US11081908
申请日：2005-03-15
申请人： Pooi Lee , Kin Pey , Alex See , Lap Chan
发明人： Pooi Lee , Kin Pey , Alex See , Lap Chan
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/49 , H01L27/095
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

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