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1. 发明申请

US20040151120A1 Fast-path implementation for a double tagging loopback engine 失效
标题翻译：双标签环回引擎的快速路径实现
公开(公告)号：US20040151120A1
公开(公告)日：2004-08-05
申请号：US10358315
申请日：2003-02-05
申请人： Broadcom Corporation
发明人： Laxman Shankar , Shekhar Ambe
IPC分类号： H04L012/26
CPC分类号： H04L49/90
摘要： A network component for processing a packet can include a buffer configured to receive a packet, a forwarding unit configured to forward the packet received at the first buffer to a loopback port, and a transmitting unit configured to transmit the packet out of the loopback port. In addition, the network component can include a loopback unit configured to loop back the packet into the loopback port, a first identification unit configured to identify an egress port, and a second transmitting unit configured to transmit the packet looped back from the loopback port out of the egress port.
摘要翻译：用于处理分组的网络组件可以包括被配置为接收分组的缓冲器，转发单元，被配置为将在第一缓冲器处接收到的分组转发到环回端口，以及发送单元，被配置为将该分组发送出环回端口。另外，网络组件可以包括被配置为将分组环回环回端口的环回单元，被配置为识别出口端口的第一识别单元和被配置为将从环回端口返回的分组发送出去的第二发送单元的出口端口。

2. 发明申请

US20030189924A1 Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets 失效
公开(公告)号：US20030189924A1
公开(公告)日：2003-10-09
申请号：US10418280
申请日：2003-04-18
申请人： Broadcom Corporation
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L012/66
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. A plurality of semiconductor-implemented lookup tables are provided, with the lookup tables including an address resolution lookup/layer three lookup, rules tables, and VLAN tables. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses. An update to an address table associated with an initial data port interface of the first and second data port interfaces results in the initial data port interface sending a synchronization signal to the other address resolution tables in the network switch. As a result, all address resolution tables on the network switch are synchronized on a per entry basis.

3. 发明申请

US20020093974A1 High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory 有权
公开(公告)号：US20020093974A1
公开(公告)日：2002-07-18
申请号：US10100078
申请日：2002-03-19
申请人： Broadcom Corporation
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L012/56 , H04L012/28
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port and the second data port to one of the internal memory and the external memory interface, according to a predetermined algorithm.

4. 发明申请

US20020034187A1 Network switch having port blocking capability 有权
标题翻译：网络交换机具有端口阻塞能力
公开(公告)号：US20020034187A1
公开(公告)日：2002-03-21
申请号：US09953881
申请日：2001-09-18
申请人： Broadcom Corporation
发明人： Mohan Kalkunte , Shekhar Ambe , Sam Sampath
IPC分类号： H04L012/28 , H04L012/66
CPC分类号： H04L49/3009 , H04L49/351 , H04L49/354 , H04L49/357
摘要： A switch is configured to block packets from being transmitted through designated ports. The switch has port bitmap generator configured to obtain a port bitmap and a table is configured to store a block mask indicating which port the packet should not be transmitted. A block mask lookup is configured to determine the block mask for the packet from the table, and a transmit port bitmap generator is configured to determine which ports the packet should be transmitted using the port bitmap and the block mask.
摘要翻译：交换机被配置为阻止通过指定端口传输数据包。交换机具有端口位图生成器，其被配置为获得端口位图，并且表被配置为存储指示哪个端口不应该发送该分组的块掩码。块掩模查找被配置为确定来自表的分组的块掩码，并且发送端口位图生成器被配置为使用端口位图和块掩码来确定应该发送数据包的哪些端口。

5. 发明申请

US20020012345A1 Cascading of gigabit switches 失效
标题翻译：千兆交换机级联
公开(公告)号：US20020012345A1
公开(公告)日：2002-01-31
申请号：US09877013
申请日：2001-06-11
申请人： BROADCOM CORPORATION
发明人： Mohan Kalkunte , Shekhar Ambe
IPC分类号： H04L012/28
CPC分类号： H04L47/2458 , H04L12/462 , H04L45/00 , H04L45/16 , H04L45/245 , H04L45/52 , H04L45/742 , H04L47/10 , H04L47/266 , H04L47/29 , H04L47/32 , H04L49/102 , H04L49/109 , H04L49/15 , H04L49/3009 , H04L49/3018 , H04L49/3036 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/506 , H04L49/508 , H04L49/602 , H04L69/22 , Y02D50/30
摘要： A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.
摘要翻译：在一系列网络交换机中处理数据分组的方法包括在一系列网络交换机的第一交换机的数据端口处接收输入数据分组。解析输入数据包的模块ID位图，并检查对应于模块ID位图的第一个开关的位，以确定该位是否被置位。当对应的位被设置并且基于目的地地址转发或丢弃传入数据分组时，解析输入数据分组的目的地址。当相应位未设置时，输入数据包将被转发到一系列网络交换机的下一个交换机。还公开了配置为允许数据分组的级联的网络交换机。

6. 发明申请

US20040032869A1 Packet filtering based on port bit map 失效
标题翻译：基于端口位映射的数据包过滤
公开(公告)号：US20040032869A1
公开(公告)日：2004-02-19
申请号：US10212211
申请日：2002-08-06
申请人： Broadcom Corporation
发明人： Shekhar Ambe , Sandeep Kumar Relan
IPC分类号： H04L012/28 , H04L012/56
CPC分类号： H04L49/30 , H04L45/26 , H04L49/35
摘要： A network device for processing a packet can have at least one port within the network device configured to received or transmit a packet, and a storage unit configured to store a port bit map, wherein the port bit map corresponds to the at least one port. Furthermore, the network device for processing a packet can have a rules table configured to have at least one port match entry and at least one action corresponding to the at least one port match entry therein, and a control unit configured to compare the port bit map with the at least one port match entry, and to implement the at least one action when a first positive value results from comparing the port bit map with the port match entry.
摘要翻译：用于处理分组的网络设备可以具有被配置为接收或发送分组的网络设备内的至少一个端口，以及被配置为存储端口比特图的存储单元，其中端口比特图对应于至少一个端口。此外，用于处理分组的网络设备可以具有被配置为具有与其中的至少一个端口匹配条目相对应的至少一个端口匹配条目和至少一个动作的规则表，以及被配置为将端口比特图至少一个端口匹配条目，并且当通过将端口比特图与端口匹配条目进行比较而产生第一正值时，实现至少一个动作。

7. 发明申请

US20030179754A1 Two stage egress scheduler for a network device 审中-公开
标题翻译：网络设备的两级出口调度器
公开(公告)号：US20030179754A1
公开(公告)日：2003-09-25
申请号：US10247299
申请日：2002-09-20
申请人： Broadcom Corporation
发明人： Laxman Shankar , Shekhar Ambe
IPC分类号： H04L012/28
CPC分类号： H04L47/10 , H04L12/56
摘要： A network device for network communications is disclosed. The device includes at least one data port interface, the at least one data port interface supporting at least one ingress data port receiving data and at least one egress port transmitting data. The device also includes a memory communicating with the at least one data port interface and a memory management unit including a memory interface for communicating data from the at least one data port interface and the memory. The memory management unit comprises a scheduler and a prefetch scheduler and the memory comprises at least two queues for containing packet data. Additionally, the prefetch scheduler is configured to fetch packet data from a first queue of the at least two queues and placing the packet data on a second queue of the at least two queues and the scheduler is configured to fetch packet data from the second queue and send the packet data to the at least one egress port.
摘要翻译：公开了一种用于网络通信的网络设备。所述设备包括至少一个数据端口接口，所述至少一个数据端口接口支持至少一个入口数据端口接收数据，以及至少一个出口端口发送数据。该设备还包括与至少一个数据端口接口通信的存储器和包括用于从至少一个数据端口接口和存储器传送数据的存储器接口的存储器管理单元。存储器管理单元包括调度器和预取调度器，并且存储器包括用于包含分组数据的至少两个队列。另外，预取调度器被配置为从至少两个队列的第一队列获取分组数据，并且将分组数据放置在至少两个队列的第二队列上，并且调度器被配置为从第二队列获取分组数据，并且将分组数据发送到至少一个出口端口。

8. 发明申请

US20030174705A1 Multilevel parser for conditional flow detection in a network device 有权
标题翻译：用于网络设备中条件流检测的多级解析器
公开(公告)号：US20030174705A1
公开(公告)日：2003-09-18
申请号：US10234267
申请日：2002-09-05
申请人： Broadcom Corporation
发明人： Laxman Shankar , Shekhar Ambe
IPC分类号： H04L012/28
CPC分类号： H04L63/0236 , H04L45/742 , H04L63/0245
摘要： A process of filtering packet data in a network device is disclosed. A descriptor table is accessed to obtain a first descriptor and a first field is extracted from a packet based on the first descriptor. An action table is accessed based on a value of the first field of the packet. Then an action from the action table is executed when a valid bit from the action table for the action is set or an action from a miss action table is executed when a valid bit from the action table for the action is not set.
摘要翻译：公开了一种过滤网络设备中的分组数据的过程。访问描述符表以获得第一描述符，并且基于第一描述符从分组中提取第一字段。基于分组的第一个字段的值来访问动作表。然后，当来自动作的动作表中的有效位被设置或来自错误动作表的动作被执行时，当来自动作的动作表中的有效位未设置时，执行动作表的动作。

9. 发明申请

US20020034181A1 Switch assembly having multiple blades in a chassis 有权
标题翻译：开关组件在机箱中具有多个刀片
公开(公告)号：US20020034181A1
公开(公告)日：2002-03-21
申请号：US09956020
申请日：2001-09-20
申请人： Broadcom Corporation
发明人： Mohan Kalkunte , Shekhar Ambe
IPC分类号： H04L012/28
CPC分类号： H04L43/00 , H04L43/12 , H04L49/3018 , H04L49/351 , H04L49/354
摘要： A switch assembly having multiple blades in a chassis and a method of using that assembly to switch data is disclosed. A network switch assembly for network communications includes at least one fabric blade and a plurality of port blades. The at least one fabric blade has at least one switch having a plurality of data port interfaces, supporting a plurality of fabric data ports transmitting and receiving data, and a CPU interface, where CPU interface is configured to communicate with a CPU. The at least one fabric blade also has a CPU subsystem communicating with the CPU interface. Each of said plurality of port blades has at least one switch having a plurality of data port interfaces, supporting a plurality of port data ports transmitting and receiving data. The plurality of port data ports communicate with the plurality of fabric data ports along multiple paths such that data received by the port data ports is switched to a destination port of the network switch assembly along a specified path of the multiple paths based on a portion of the received data. In particular, the invention relates to configurations having five and nine blades to provide the requisite switching capacity.
摘要翻译：公开了一种在底盘中具有多个叶片的开关组件以及使用该组件切换数据的方法。用于网络通信的网络交换机组件包括至少一个结构刀片和多个端口刀片。至少一个织物刀片具有至少一个开关，其具有多个数据端口接口，支持多个结构数据端口发送和接收数据;以及CPU接口，其中CPU接口被配置为与CPU通信。至少一个织物刀片还具有与CPU接口通信的CPU子系统。所述多个端口刀片中的每一个具有至少一个具有多个数据端口接口的开关，支持多个端口数据端口发送和接收数据。多个端口数据端口沿着多个路径与多个结构数据端口进行通信，使得由端口数据端口接收的数据沿着多个路径的指定路径被切换到网络交换机组件的目的地端口收到的数据。特别地，本发明涉及具有五个和九个刀片以提供必要的切换能力的配置。

10. 发明申请

US20020031090A1 High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory 失效
标题翻译：基于分布式分层共享存储器的高性能自平衡低成本网络交换架构
公开(公告)号：US20020031090A1
公开(公告)日：2002-03-14
申请号：US09985251
申请日：2001-11-02
申请人： Broadcom Corporation
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04J003/24
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port and the second data port to one of the internal memory and the external memory interface, according to a predetermined algorithm.
摘要翻译：用于网络通信的数据交换机包括支持以第一数据速率发送和接收数据的多个数据端口的至少一个第一数据端口接口。提供至少一个第二数据端口接口; 所述至少一个第二数据端口接口支持以第二数据速率发送和接收数据的多个数据端口。提供了CPU接口，CPU接口配置为与CPU进行通信。提供内部存储器，并与至少一个第一数据端口接口和至少一个第二数据端口接口进行通信。提供存储器管理单元，并且包括用于从第一数据端口接口和第二数据端口接口中的至少一个传送数据的外部存储器接口和外部存储器。提供通信信道，通信信道在至少一个第一数据端口接口，至少一个第二数据端口接口，内部存储器和存储器管理单元之间传送数据和消息传递信息。根据预定算法，存储器管理单元将数据从第一数据端口和第二数据端口之一引导到内部存储器和外部存储器接口之一。

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