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1. 发明授权

US08332580B2 System, method and apparatus for memory with embedded associative section for computations 有权
标题翻译：用于计算的嵌入式联想部分的存储器的系统，方法和装置
公开(公告)号：US08332580B2
公开(公告)日：2012-12-11
申请号：US12464937
申请日：2009-05-13
申请人： Avidan Akerib , Eli Ehrman , Josh Meir , Moshe Meyassed , Oren Agam , Yair Alpern
发明人： Avidan Akerib , Eli Ehrman , Josh Meir , Moshe Meyassed , Oren Agam , Yair Alpern
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
摘要翻译：集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据并且对数据执行关联计算。

2. 发明授权

US08341362B2 System, method and apparatus for memory with embedded associative section for computations 有权
标题翻译：用于计算的嵌入式联想部分的存储器的系统，方法和装置
公开(公告)号：US08341362B2
公开(公告)日：2012-12-25
申请号：US12650604
申请日：2009-12-31
申请人： Avidan Akerib , Eli Ehrman , Moshe Meyassed , Oren Agam
发明人： Avidan Akerib , Eli Ehrman , Moshe Meyassed , Oren Agam
IPC分类号： G06F13/00 , G06F13/28 , G09G5/36
CPC分类号： G11C7/1006 , G09G5/06 , G09G5/393
摘要： A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.
摘要翻译：一种用于数据处理的系统和方法，所述方法包括：以行方式将输入数据字存储在包括以行和列排列的多个存储单元的存储器中; 以及通过执行移位操作和关联操作的顺序来转置多个数据字; 其中关联操作包括将多个相关联存储器单元并行至少一个比较; 并将转置的数据字存储在存储器中。

3. 发明授权

US08908465B2 Using storage cells to perform computation 有权
标题翻译：使用存储单元执行计算
公开(公告)号：US08908465B2
公开(公告)日：2014-12-09
申请号：US13437955
申请日：2012-04-03
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C8/00 , G11C15/04 , G11C29/34
CPC分类号： G11C29/34 , G11C15/043
摘要： A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.
摘要翻译：内容可寻址存储器（CAM）单元没有任何单元内比较器电路。 CAM单元包括存储器阵列，多行解码器，控制器和输出单元。存储器阵列具有排列成数据行和补码行的存储单元。多行解码器一次激活多于一行存储器阵列，并且控制器向多行解码器指示作为要匹配的输入模式的函数来激活数据行或补码行。输出单元指示哪些列生成信号，列与模式匹配。

4. 发明授权

US08238173B2 Using storage cells to perform computation 有权
标题翻译：使用存储单元执行计算
公开(公告)号：US08238173B2
公开(公告)日：2012-08-07
申请号：US12503916
申请日：2009-07-16
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.
摘要翻译：存储器内部处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了没有任何单元内比较器电路的内容可寻址存储器（CAM）单元。

5. 发明授权

US09076527B2 Charge sharing in a TCAM array 有权
标题翻译： TCAM阵列中的电荷共享
公开(公告)号：US09076527B2
公开(公告)日：2015-07-07
申请号：US13233065
申请日：2011-09-15
申请人： Oren Agam , Avidan Akerib , Eli Ehrman , Moshe Meyassed
发明人： Oren Agam , Avidan Akerib , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C15/00 , G11C15/04 , G11C8/08 , G11C8/10 , G11C7/10 , G11C11/403
CPC分类号： G11C15/043 , G11C7/1006 , G11C8/08 , G11C8/10 , G11C11/403
摘要： A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.
摘要翻译：存储单元包括存储电容器，读取线路和存储晶体管，其中存储晶体管连接到读取线并且通过存储电容器中的电荷进行激活。存储器内存处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少该数据的布尔函数输出两个单元，其中所述至少两个单元中的每一个至少包括存储电容器，存储晶体管和读取线，其中所述存储晶体管连接到所述读取线并通过所述存储电容器中的电荷进行激活。

6. 发明授权

US08711638B2 Using storage cells to perform computation 有权
标题翻译：使用存储单元执行计算
公开(公告)号：US08711638B2
公开(公告)日：2014-04-29
申请号：US13437956
申请日：2012-04-03
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C7/10 , G11C29/34
CPC分类号： G11C29/34 , G11C15/043
摘要： A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.
摘要翻译：一种方法包括激活至少两行纯存储器单元并读取激活的存储器单元的至少一列，该读取产生存储在激活的存储单元中的数据的二进制函数。

7. 发明申请

US20120246380A1 NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING 审中-公开
标题翻译：并行处理的邻里操作
公开(公告)号：US20120246380A1
公开(公告)日：2012-09-27
申请号：US13502797
申请日：2010-10-06
申请人： Avidan Akerib , Eli Ehrman , Oren Agam , Moshe Meyassed , Yehoshua Meir , Yukio Fukuzo
发明人： Avidan Akerib , Eli Ehrman , Oren Agam , Moshe Meyassed , Yehoshua Meir , Yukio Fukuzo
IPC分类号： G06F12/06
CPC分类号： G11C7/1006
摘要： A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
摘要翻译：一种存储装置包括多个存储单元，用于存储存储体的数据，其中该数据具有在存储之前的逻辑顺序和与该多个存储单元内的逻辑顺序不同的物理顺序，以及一个设备内重排序单元在执行片上处理之前将存储体的数据重新排列成逻辑顺序。在另一个实施例中，存储设备包括可连接到与存储器设备通信的外部设备的外部设备接口，用于处理存储在设备上的数据和多组存储器的内部处理元件。每个存储体包括多个存储单元，每个存储单元具有两个端口，可连接到外部设备接口的外部端口和连接到内部处理元件的内部端口。

8. 发明申请

US20110013442A1 USING STORAGE CELLS TO PERFORM COMPUTATION 有权
标题翻译：使用储存细胞进行计算
公开(公告)号：US20110013442A1
公开(公告)日：2011-01-20
申请号：US12503916
申请日：2009-07-16
申请人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
发明人： Avidan Akerib , Oren Agam , Eli Ehrman , Moshe Meyassed
IPC分类号： G11C15/00 , G11C7/00 , G11C8/00
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.
摘要翻译：存储器内部处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了没有任何单元内比较器电路的内容可寻址存储器（CAM）单元。

9. 发明申请

US20090254697A1 MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS 审中-公开
标题翻译：用于计算的嵌入式相关部分的内存
公开(公告)号：US20090254697A1
公开(公告)日：2009-10-08
申请号：US12119197
申请日：2008-05-12
申请人： Avidan Akerib , Eli Ehrman , Yoav Lavi , Moshe Meyassed
发明人： Avidan Akerib , Eli Ehrman , Yoav Lavi , Moshe Meyassed
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
摘要翻译：集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据并且对数据执行关联计算。

10. 发明申请

US20120246401A1 IN-MEMORY PROCESSOR 审中-公开
标题翻译：内存处理器
公开(公告)号：US20120246401A1
公开(公告)日：2012-09-27
申请号：US13502783
申请日：2010-10-21
申请人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
发明人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.
摘要翻译：存储器件包括至少两个存储数据的存储体和内部处理器。至少两个存储体可由主处理器访问。内部处理器从主机处理器接收时隙，并且在时隙期间处理来自存储器阵列的至少两个存储体组中指定的一个的数据的一部分，而在时隙期间剩余的存储体可用于主机处理器。一种操作具有存储数据的存储器的存储器件的方法包括：主处理器，每个存储体时隙向存储器件的内部处理器发出，所述内部处理器在时隙期间在存储器件的指示库上操作，并且主机处理器不访问存储器在时间段内指定银行。

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