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    • 2. 发明授权
    • Associative processor
    • 关联处理器
    • US06711665B1
    • 2004-03-23
    • US09572581
    • 2000-05-17
    • Avidan AkeribJosh MeirRonen StilkolYaron Serfati
    • Avidan AkeribJosh MeirRonen StilkolYaron Serfati
    • G06F1580
    • G06F15/8038
    • An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays. The tags logic block supports operations such as logical combinations of match result signals from the CAM cell arrays and the contents of one of the tags registers, with storage of the results in the same tags register or in a different tags register; and also concatenation of two tags registers, with a shift operation applied to the concatenated tags registers resulting in a partial transfer of the contents of one tags register to the other tags register.
    • 关联处理器包括多个内容可寻址存储器(CAM)单元阵列和标签逻辑块中的多个标签寄存器。 不同的标签寄存器随意地与不同的CAM单元阵列相关联,以支持在两个或更多个CAM单元阵列上并行执行相同或不同的算术运算,并且通过使两个CAM单元阵列共享一个标记寄存器来传送来支持流水线算术运算 数据从一个CAM单元阵列到另一个使用适当的比较和写操作。 所有CAM单元阵列共享相同的掩码和模式寄存器。 优选地,至少一个标签寄存器物理地位于两个CAM单元阵列之间。 标签逻辑块支持诸如来自CAM单元阵列的匹配结果信号和一个标签寄存器的内容的逻辑组合的操作,将结果存储在相同的标签寄存器或不同的标签寄存器中; 并且还连接两个标签寄存器,其中移位操作被应用于级联标签寄存器,导致将一个标签寄存器的内容部分地传送到其他标签寄存器。