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1. 发明申请

US20120246380A1 NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING 审中-公开
标题翻译：并行处理的邻里操作
公开(公告)号：US20120246380A1
公开(公告)日：2012-09-27
申请号：US13502797
申请日：2010-10-06
申请人： Avidan Akerib , Eli Ehrman , Oren Agam , Moshe Meyassed , Yehoshua Meir , Yukio Fukuzo
发明人： Avidan Akerib , Eli Ehrman , Oren Agam , Moshe Meyassed , Yehoshua Meir , Yukio Fukuzo
IPC分类号： G06F12/06
CPC分类号： G11C7/1006
摘要： A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
摘要翻译：一种存储装置包括多个存储单元，用于存储存储体的数据，其中该数据具有在存储之前的逻辑顺序和与该多个存储单元内的逻辑顺序不同的物理顺序，以及一个设备内重排序单元在执行片上处理之前将存储体的数据重新排列成逻辑顺序。在另一个实施例中，存储设备包括可连接到与存储器设备通信的外部设备的外部设备接口，用于处理存储在设备上的数据和多组存储器的内部处理元件。每个存储体包括多个存储单元，每个存储单元具有两个端口，可连接到外部设备接口的外部端口和连接到内部处理元件的内部端口。

2. 发明申请

US20120246401A1 IN-MEMORY PROCESSOR 审中-公开
标题翻译：内存处理器
公开(公告)号：US20120246401A1
公开(公告)日：2012-09-27
申请号：US13502783
申请日：2010-10-21
申请人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
发明人： Oren Agam , Moshe Meyassed , Yukio Fukuzo
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.
摘要翻译：存储器件包括至少两个存储数据的存储体和内部处理器。至少两个存储体可由主处理器访问。内部处理器从主机处理器接收时隙，并且在时隙期间处理来自存储器阵列的至少两个存储体组中指定的一个的数据的一部分，而在时隙期间剩余的存储体可用于主机处理器。一种操作具有存储数据的存储器的存储器件的方法包括：主处理器，每个存储体时隙向存储器件的内部处理器发出，所述内部处理器在时隙期间在存储器件的指示库上操作，并且主机处理器不访问存储器在时间段内指定银行。

3. 发明授权

US07356654B2 Flexible multi-area memory and electronic device using the same 有权
标题翻译：灵活的多区域内存和电子设备使用相同
公开(公告)号：US07356654B2
公开(公告)日：2008-04-08
申请号：US11074726
申请日：2005-03-09
申请人： Yukio Fukuzo
发明人： Yukio Fukuzo
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C11/4076 , G11C11/4087 , G11C11/4097 , G11C2211/4013
摘要： A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by the first and the second processors. The common area has two ports and thereby simultaneously accessible from the first and the second processors. Each capacity of the first, the second, and the common areas can be set arbitrarily.
摘要翻译：用于诸如移动电话的电子设备的灵活多区域存储器包括具有给定容量的存储区域。存储区域具有仅由第一处理器访问的第一区域，仅由第二处理器访问的第二区域和由第一处理器和第二处理器共享的公共区域。公共区域具有两个端口，从而可以从第一和第二处理器同时访问。第一，第二和公共区域的容量可以任意设定。

4. 发明授权

US5341341A Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture 失效
标题翻译：具有布置在管道架构中的寻址部分和/或数据传送路径的动态随机存取存储器件
公开(公告)号：US5341341A
公开(公告)日：1994-08-23
申请号：US36031
申请日：1993-03-23
申请人： Yukio Fukuzo
发明人： Yukio Fukuzo
IPC分类号： G11C11/407 , G11C7/10 , G11C11/4096 , G11C11/413 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4096 , G11C7/1039
摘要： A dynamic random access memory device is responsive to a row address signal and a column address signal supplied in synchronism with a system clock signal for providing a data path from a data input/output port and a memory cell selected from the memory cell array, and latch circuits are provided in the addressing section and the data transferring path for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.
摘要翻译：动态随机存取存储器件响应于与系统时钟信号同步提供的行地址信号和列地址信号，用于从数据输入/输出端口和从存储单元阵列中选择的存储单元提供数据路径;以及响应于比系统时钟信号更高的锁存控制信号，在寻址部分和数据传送路径中提供锁存电路，用于临时存储地址解码信号和写入和读出数据位，从而控制数据流管道时尚。

5. 发明授权

US4695980A Integrated circuit having a common input terminal 失效
标题翻译：具有公共输入端的集成电路
公开(公告)号：US4695980A
公开(公告)日：1987-09-22
申请号：US753091
申请日：1985-07-09
申请人： Yukio Fukuzo , Yasukazu Inoue
发明人： Yukio Fukuzo , Yasukazu Inoue
IPC分类号： H03K17/687 , G11C5/06 , G11C7/10 , G11C11/406 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G11C11/406 , G11C5/066 , G11C7/1006
摘要： An improved integrated circuit provided with a reduced capacitance of common external terminal connected to a plurality of circuits is disclosed. A switch is inserted between the external terminal and at least one of the circuits. The switch is controlled in such manner that it is rendered conductive when that circuit is to receive the signal at the external terminal and non-conductive when the circuit is not to receive the signal at the external terminal therein.
摘要翻译：公开了一种改进的集成电路，其具有连接到多个电路的公共外部端子的减小的电容。在外部端子和至少一个电路之间插入开关。开关被控制为当该电路在外部端子处接收信号时导通，并且在电路不在其外部端子处接收信号时导通。

6. 发明申请

US20050170600A1 Three-dimensional semiconductor package, and spacer chip used therein 审中-公开
标题翻译：三维半导体封装和其中使用的间隔芯片
公开(公告)号：US20050170600A1
公开(公告)日：2005-08-04
申请号：US11045378
申请日：2005-01-31
申请人： Yukio Fukuzo
发明人： Yukio Fukuzo
IPC分类号： H01L25/18 , H01L21/20 , H01L21/822 , H01L23/52 , H01L25/04 , H01L25/065 , H01L25/07 , H01L27/04
CPC分类号： H01L25/0657 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2924/01004 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： In a three-dimensional semiconductor package, a logic-circuit chip has a plurality of top electrode terminals formed on a top surface thereof, and a spacer chip is mounted on the logic-circuit chip. The spacer chip has a plurality of bottom electrode terminals formed on a bottom surface thereof, and a plurality of top electrode terminals formed on a top surface thereof and electrically connected to the respective bottom electrode terminals thereof. The mounting of the spacer chip on the logic-circuit chip is carried out such that the bottom electrode terminals of the spacer chip are bonded to the top electrode terminals of the logic-circuit chip, to thereby establish electrical connections therebetween. A memory chip is mounted on the spacer chip, and has a plurality of electrode terminals formed on a surface thereof. The mounting of the memory chip on the spacer chip is carried out such that the electrode terminals of the memory chip are bonded to the top electrode terminals of the spacer chip, to thereby establish electrical connections therebetween.
摘要翻译：在三维半导体封装中，逻辑电路芯片具有形成在其顶表面上的多个顶电极端子，并且间隔芯片安装在逻辑电路芯片上。间隔芯片具有形成在其底面上的多个底部电极端子和形成在其顶表面上并与其各自底部电极端子电连接的多个顶部电极端子。隔离芯片在逻辑电路芯片上的安装被执行为使得间隔芯片的底部电极端子接合到逻辑电路芯片的顶部电极端子，从而在它们之间建立电气连接。存储芯片安装在间隔片上，并且在其表面上形成有多个电极端子。存储芯片在间隔片上的安装被执行，使得存储芯片的电极端子接合到间隔片的顶电极端子，从而在它们之间建立电连接。

7. 发明授权

US6154385A Semiconductor memory with built-in row buffer and method of driving the same 有权
标题翻译：具有内置行缓冲器和驱动方式的半导体存储器
公开(公告)号：US6154385A
公开(公告)日：2000-11-28
申请号：US163169
申请日：1998-09-30
申请人： Yukio Fukuzo
发明人： Yukio Fukuzo
IPC分类号： G11C11/408 , G11C7/10 , G11C16/02 , G11C16/06 , E11C8/00
CPC分类号： G11C7/1051
摘要： There is provided a semiconductor memory including a plurality of sub-arrays each of which includes a plurality of cells arranged in a matrix, at least one word line connected to gates of cells arranged in a first direction among the cells, at least one bit line for providing a data-writing signal to one of electrodes of cells arranged in a second direction among the cells, the second direction being perpendicular to the first direction, at least one ground line for reading data out of the other of the electrodes of cells arranged in the second direction, a plurality of sense-amplifiers associated with each of the sub-arrays for providing a sense-amplifying current to the bit line, and a plurality of row buffers connected to all of the sub-arrays for retaining data of a cell selected by the word line. In accordance with the above-mentioned semiconductor memory, a plurality of row buffers for retaining data stored in cells in a sub-array selected by a word line are connected to all of the sub-arrays. Hence, it is possible to reduce internal I/O buses, which further makes it possible to avoid that a semiconductor chip is increased in size because of an increase of internal I/O buses. In addition, since it is no longer necessary to form a three-layered aluminum structure, a fabrication cost can be suppressed from increasing. Furthermore, since data transmission can be conducted between row buffers and external circuits, a data transmission speed can be enhanced.
摘要翻译：提供了一种包括多个子阵列的半导体存储器，每个子阵列包括以矩阵形式布置的多个单元，至少一个字线连接到在单元中沿第一方向布置的单元的栅极，至少一个位线用于向所述单元之间沿第二方向布置的单元的电极中的一个电极提供数据写入信号，所述第二方向垂直于所述第一方向;至少一个接地线，用于从排列的单元电极中的另一个电极读出数据在第二方向上，与用于向位线提供感测放大电流的每个子阵列相关联的多个读出放大器，以及连接到所有子阵列的多个行缓冲器，用于保留单元格选中的单元格。根据上述半导体存储器，用于保存存储在由字线选择的子阵列中的单元中的数据的多个行缓冲器连接到所有子阵列。因此，可以减少内部I / O总线，这进一步使得可以避免由于内部I / O总线的增加而导致半导体芯片的尺寸增加。此外，由于不再需要形成三层铝结构，因此可以抑制制造成本的增加。此外，由于可以在行缓冲器和外部电路之间进行数据传输，因此可以提高数据传输速度。

8. 发明授权

US5495454A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5495454A
公开(公告)日：1996-02-27
申请号：US159233
申请日：1993-11-30
申请人： Yukio Fukuzo
发明人： Yukio Fukuzo
IPC分类号： G11C11/41 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C11/408
摘要： A memory device comprises a plurality of memory cell array blocks (CAB1) each having at least one word line (WL11) and associated with a word line drive circuit (PD1a, WD1a, RD1), a block select circuit (BSa) for selectively outputting a block select signal (SL1s) corresponding to one of the memory cell array blocks, an address buffer (AB1a) for outputting word address signals (AddR1) to the memory cell array blocks wherein the word line drive circuit is associated with an address latch circuit (AL1a) which latches and continuously outputs one of the word address signals thereto, the block select signal activates the address latch circuit for latching one of the word address signals, the word line drive circuit continuously activates the word line according to an output signal (AL1aout) of the address latch circuit and deactivates the word line only when the block select signal (SL1s) corresponding to the memory cell array block is output from the block select circuit.
摘要翻译：存储器件包括多个存储单元阵列块（CAB1），每个存储单元阵列块具有至少一个字线（WL11）并与字线驱动电路（PD1a，WD1a，RD1）相关联，块选择电路（BSa）用于选择性地输出对应于一个存储单元阵列块的块选择信号（SL1s），用于将字地址信号（AddR1）输出到存储单元阵列块的地址缓冲器（AB1a），其中字线驱动电路与地址锁存电路（AL1a），其锁存并连续地输出字地址信号之一，块选择信号激活用于锁存字地址信号之一的地址锁存电路，字线驱动电路根据输出信号连续地激活字线（ AL1aout），并且仅当与块选择电路输出与存储单元阵列块相对应的块选择信号（SL1s）时才停用字线。

9. 发明授权

US07415581B2 Semiconductor memory chip 失效
标题翻译：半导体存储芯片
公开(公告)号：US07415581B2
公开(公告)日：2008-08-19
申请号：US11242149
申请日：2005-10-04
申请人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmölz
发明人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmölz
IPC分类号： G11C7/08 , G11C11/4063
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.
摘要翻译：信号作为串行信号帧传送的半导体存储器芯片包括提供存储器核心和接收接口之间的接口的帧解码器。帧解码器包括用于根据解码的命令类型对包括在帧中的命令的类型进行解码的命令类型解码器，用于调度和准备用于核心的单个命令的存储器命令评估器/生成器，中间数据缓冲器命令评估器/生成器用于调度和准备中间数据缓冲器的控制信号，以及用于准备和调度系统命令的系统命令评估器/发生器。这些系统命令提供定时参数，以确保一帧内或帧之间的连续命令之间的时间间隔，并存储在系统模式寄存器中。帧解码器的操作由帧时钟或同步解码器时钟信号进行边沿同步，该时钟信号与该帧时钟信号相对齐。

10. 发明授权

US4692642A Active pull-up circuit controlled by a single pull-up clock signal 失效
标题翻译：有源上拉电路由单个上拉时钟信号控制
公开(公告)号：US4692642A
公开(公告)日：1987-09-08
申请号：US753715
申请日：1985-07-10
申请人： Yukio Fukuzo , Yasukazu Inoue
发明人： Yukio Fukuzo , Yasukazu Inoue
IPC分类号： G11C11/409 , G11C11/4094 , H03K3/356 , H03K19/017
CPC分类号： H03K3/35606 , G11C11/4094 , H03K19/01742 , H03K3/356095
摘要： An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.
摘要翻译：一种改进的有源上拉电路，其可以以较少数量的元件制造并且以小的功耗进行操作。在刷新电压端子和要上拉的真实电路节点之间设置第一开关。提供由互补电路节点的电位控制的第二开关用于可操作地放电第一开关的控制电极的电荷。通过电容器将上拉时钟施加到第一开关的控制电极。

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