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1. 发明授权

US06900092B2 Surface engineering to prevent epi growth on gate poly during selective epi processing 失效
标题翻译：表面工程，以防止在选择性epi处理期间在栅极poly上的epi生长
公开(公告)号：US06900092B2
公开(公告)日：2005-05-31
申请号：US10183336
申请日：2002-06-27
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78 , H01L21/8238 , H01L21/31 , H01L21/3205
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

2. 发明授权

US06440807B1 Surface engineering to prevent EPI growth on gate poly during selective EPI processing 有权
标题翻译：表面工程，以防止EPI在选择性EPI加工过程中对聚酰胺的生长
公开(公告)号：US06440807B1
公开(公告)日：2002-08-27
申请号：US09882095
申请日：2001-06-15
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21336
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

3. 发明授权

US06602759B2 Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon 有权
公开(公告)号：US06602759B2
公开(公告)日：2003-08-05
申请号：US09731620
申请日：2000-12-07
申请人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
发明人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
IPC分类号： H01L2176
CPC分类号： H01L21/76227
摘要： A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench. Alternatively, either a doped polysilicon layer or a doped SiO2 layer may be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure is heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. The doped layers are then removed by selective wet etching and expose the silicon nitride layer prior to oxidation.

4. 发明授权

US06506649B2 Method for forming notch gate having self-aligned raised source/drain structure 有权
标题翻译：用于形成具有自对准凸起源极/漏极结构的陷波栅的方法
公开(公告)号：US06506649B2
公开(公告)日：2003-01-14
申请号：US09811706
申请日：2001-03-19
申请人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
发明人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance. The method of constructing such a structure includes the steps of: forming a notch gate on a top surface of a substrate; covering the notch gate and the top surface of the substrate with a conformal dielectric film; etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; implanting doping to form a drain-source area; forming spacers on the vertical walls of the notch gate; and forming a salicide on the notch gate and on the source and drain areas. The MOSFET device may be alternately be built without the formation of spacers.
摘要翻译：在植入源极 - 漏极掺杂剂之前，构建了具有升高的源极漏极（RSD）的创新型MOSFET。如此构建的RSD结构具有明显的优点，即从RSD到MOSFET通道的偏移是完全可调的，以最小化器件中的重叠电容。 RSD结构使用选择性外延工艺来有效降低漏极 - 源极电阻。这种改进在薄膜SOI技术中更为显着。使用RSD，通道区域外部的膜变厚，这又降低了寄生电阻。构造这种结构的方法包括以下步骤：在衬底的顶表面上形成陷波门; 用保形绝缘膜覆盖基板的切口栅和顶表面; 蚀刻电介质膜以暴露陷波栅的上表面和基板的选定的曝光区域; 选择性地在栅极刻蚀的蚀刻表面上和衬底的蚀刻表面上生长硅; 注入掺杂以形成漏 - 源区; 在凹口门的垂直壁上形成间隔物; 并在凹口门和源极和漏极区域上形成自对准硅化物。可以交替地构建MOSFET器件而不形成间隔物。

5. 发明授权

US06437377B1 Low dielectric constant sidewall spacer using notch gate process 失效
标题翻译：低介电常数侧壁间隔板采用切口浇口工艺
公开(公告)号：US06437377B1
公开(公告)日：2002-08-20
申请号：US09768525
申请日：2001-01-24
申请人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
发明人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
IPC分类号： H01L2710
CPC分类号： H01L29/4991 , H01L21/28114 , H01L21/28194 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/6656 , H01L29/6659
摘要： A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.
摘要翻译：缺口门MOS器件包括封装的低介电材料或封装的空气或在缺口栅极的底部的真空。由于栅极和源极/漏极之间的界面位置处的介电常数低，所以该位置处的电容损耗显着降低。

6. 发明申请

US20120228716A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 审中-公开
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20120228716A1
公开(公告)日：2012-09-13
申请号：US13478400
申请日：2012-05-23
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.
摘要翻译：包括在NFET的沟道中具有嵌入硅锗（SiGe）插头的NFET的结构; 具有SiGe沟道的PFET; 以及在NFET和PFET之间的沟槽隔离，其中NFET和PFET没有SiGe外延生长边缘效应。

7. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

8. 发明申请

US20090294801A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 失效
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20090294801A1
公开(公告)日：2009-12-03
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092 , H01L21/205 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

9. 发明授权

US07115463B2 Patterning SOI with silicon mask to create box at different depths 失效
标题翻译：用硅掩模图案化SOI以在不同深度创建盒子
公开(公告)号：US07115463B2
公开(公告)日：2006-10-03
申请号：US10923246
申请日：2004-08-20
申请人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.
摘要翻译：本发明提供一种制造图案化的绝缘体上硅衬底的方法，其包括双重深度SOI区域或同一衬底内的SOI和非SOI区域。本发明的方法包括在含Si材料的表面上形成具有至少一个开口的硅掩模，通过使用蚀刻工艺使含Si材料通过至少一个开口凹陷，以提供具有至少一个凹部区域和非凹陷区域，并且在凹陷区域中形成第一掩埋绝缘区域和凹陷区域中的第二掩埋绝缘区域。根据本发明，非凹陷区域中的第一掩埋绝缘区域位于凹陷区域中的第二掩埋隔离区域的上方。可以采用剥离步骤去除第一掩埋绝缘区域和位于上方的材料，以提供包含SOI和非SOI区域的衬底。

10. 发明授权

US08685845B2 Epitaxial growth of silicon doped with carbon and phosphorus using hydrogen carrier gas 有权
标题翻译：使用氢气载气使碳和磷掺杂的硅的外延生长
公开(公告)号：US08685845B2
公开(公告)日：2014-04-01
申请号：US12860236
申请日：2010-08-20
申请人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
发明人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , H01L21/0237 , H01L21/02529 , H01L21/02576 , H01L21/02587 , H01L21/02636 , H01L29/045 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
摘要翻译：一种用于沉积硅碳外延膜（Si：C）的方法。在一个实施例中，该方法包括：使用由含硅烷的气体前体，含碳气体前体和正极材料构成的沉积气体前体，在半导体沉积表面上沉积n型掺杂硅碳（Si：C）型气体掺杂剂源。沉积气体前体用氢（H 2）载气引入半导体沉积表面。沉积外延膜的方法可以包括由氯化氢（HCl）气体蚀刻剂和氢（H 2）载气提供的蚀刻反应。

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