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1. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

2. 发明申请

US20110049585A1 MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATION USING AN OXYGEN PLASMA 有权
标题翻译：通过使用氧气等离子体进行钝化保持高K栅格堆叠的完整性
公开(公告)号：US20110049585A1
公开(公告)日：2011-03-03
申请号：US12848644
申请日：2010-08-02
申请人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
发明人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28247 , H01L21/0206 , H01L21/02244 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/7848
摘要： In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.
摘要翻译：在半导体器件中，通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体，可以提高氮化钛材料的完整性。氧等离子体可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁方法，而不会导致氮化钛材料的不适当的材料损失。以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

3. 发明申请

US20090294801A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 失效
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20090294801A1
公开(公告)日：2009-12-03
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092 , H01L21/205 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

4. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

5. 发明申请

US20090142891A1 MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES 审中-公开
标题翻译： CMOS器件的无缝应力记忆技术
公开(公告)号：US20090142891A1
公开(公告)日：2009-06-04
申请号：US11948849
申请日：2007-11-30
申请人： Young-Hee Kim , Jeffrey W. Sleight , Huiming Bu , Rick Carter , Mike Hargrove
发明人： Young-Hee Kim , Jeffrey W. Sleight , Huiming Bu , Rick Carter , Mike Hargrove
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/84 , H01L29/7843
摘要： In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the PFET device, wherein the silicon nitride tensile strain layer induces a tensile strain in a channel of the NFET device region; annealing to crystallize the amorphous silicon containing region, wherein the tensile strain silicon nitride layer positioned atop the PFET device confines oxygen within a channel positioned within the silicon containing substrate underlying the PFET device, wherein the oxygen within the channel shifts a threshold voltage of the PFET device towards a valence band of silicon of the silicon containing substrate; and removing the tensile strain silicon nitride layer.
摘要翻译：在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供具有PFET器件和NFET器件的含硅衬底，其中所述NFET器件包括非晶硅含硅区域; 在NFET器件和PFET器件的顶部沉积拉伸应变氮化硅层，其中氮化硅拉伸应变层在NFET器件区域的沟道中引起拉伸应变; 退火以使非晶硅含有区域结晶，其中位于PFET器件顶部的拉伸应变氮化硅层将氧气限制在位于PFET器件下面的含硅衬底内的通道内，其中通道内的氧漂移PFET的阈值电压朝向含硅衬底的硅的价带的器件; 并去除拉伸应变氮化硅层。

6. 发明申请

US20090152637A1 PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT 有权
标题翻译：具有定制电介质的PFET及相关方法和集成电路
公开(公告)号：US20090152637A1
公开(公告)日：2009-06-18
申请号：US11955491
申请日：2007-12-13
申请人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
发明人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/82385
摘要： A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
摘要翻译：公开了一种具有由其栅极堆叠中的NFET阈值电压（Vt）功函数调谐层，相关方法和集成电路部分构成的定制电介质的PFET。在一个实施例中，PFET包括n型掺杂硅阱（N阱），栅堆叠，其包括：在N阱上的掺杂带工程化PFET阈值电压（Vt）功函数调谐层; 在掺杂带工程化的PFET Vt功函数调谐层之上的定制电介质层，由掺杂带工程化的PFET Vt功函数调谐层和n型场效应晶体管（NFET）阈值上的高介电常数层构成的调整后的介电层电压（Vt）工作功能调谐层在高介电常数层上; 和NFET Vt功能调谐层上的金属。

7. 发明申请

US20120228716A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 审中-公开
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20120228716A1
公开(公告)日：2012-09-13
申请号：US13478400
申请日：2012-05-23
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.
摘要翻译：包括在NFET的沟道中具有嵌入硅锗（SiGe）插头的NFET的结构; 具有SiGe沟道的PFET; 以及在NFET和PFET之间的沟槽隔离，其中NFET和PFET没有SiGe外延生长边缘效应。

8. 发明授权

US08524591B2 Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma 有权
标题翻译：使用氧等离子体通过钝化保持高K栅极堆叠的完整性
公开(公告)号：US08524591B2
公开(公告)日：2013-09-03
申请号：US12848644
申请日：2010-08-02
申请人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
发明人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28247 , H01L21/0206 , H01L21/02244 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/7848
摘要： In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.
摘要翻译：在半导体器件中，通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体，可以提高氮化钛材料的完整性。氧等离子体可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁方法，而不会导致氮化钛材料的不适当的材料损失。以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

9. 发明授权

US08053306B2 PFET with tailored dielectric and related methods and integrated circuit 有权
标题翻译： PFET具有定制电介质及相关方法及集成电路
公开(公告)号：US08053306B2
公开(公告)日：2011-11-08
申请号：US11955491
申请日：2007-12-13
申请人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
发明人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/82385
摘要： A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
摘要翻译：公开了一种具有由其栅极堆叠中的NFET阈值电压（Vt）功函数调谐层，相关方法和集成电路部分构成的定制电介质的PFET。在一个实施例中，PFET包括n型掺杂硅阱（N阱），栅堆叠，其包括：在N阱上的掺杂带工程化PFET阈值电压（Vt）功函数调谐层; 在掺杂带工程化的PFET Vt功函数调谐层之上的定制电介质层，由掺杂带工程化的PFET Vt功函数调谐层和n型场效应晶体管（NFET）阈值上的高介电常数层构成的调整后的介电层电压（Vt）工作功能调谐层在高介电常数层上; 和NFET Vt功能调谐层上的金属。

10. 发明申请

US20080176588A1 Method and System for Offloading Mobile-Originating Short Message Traffic 审中-公开
标题翻译：移动发起短消息流量的方法和系统
公开(公告)号：US20080176588A1
公开(公告)日：2008-07-24
申请号：US11683935
申请日：2007-03-08
申请人： Michael Ashdown , Steve Lynchard , Rick Carter
发明人： Michael Ashdown , Steve Lynchard , Rick Carter
IPC分类号： H04Q7/20
CPC分类号： H04W4/14 , H04W72/04
摘要： A method for managing mobile-originating short messages in a mobile communications network is provided. A request for short message service is identified in a plurality of data link connections. A subscriber is identified for the request for short message service. A radio resource is monitored for the subscriber. Short messages originating from the radio resource are offloaded for the subscriber.
摘要翻译：提供了一种在移动通信网络中管理移动发送短消息的方法。在多个数据链路连接中识别出对短消息服务的请求。为短信服务请求识别用户。监控用户的无线电资源。来自无线电资源的短消息被卸载给用户。

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