专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08551845B2 Structure and method for increasing strain in a device 有权
标题翻译：增加器件应变的结构和方法
公开(公告)号：US08551845B2
公开(公告)日：2013-10-08
申请号：US12886903
申请日：2010-09-21
申请人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
发明人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26566 , H01L21/26593 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
摘要翻译：公开了用于增加器件中应变的方法和结构，特别是n型场效应晶体管（NFET）互补金属氧化物半导体（CMOS）器件。本发明的实施例包括生长外延层，进行冷碳或簇碳预非晶化注入以将取代碳注入到外延层中，在外延层上形成拉伸帽，然后退火以使非晶层重结晶以产生应力记忆技术（SMT）效应。因此，外延层将包括取代碳并具有由SMT引起的记忆拉伸应力。本发明的实施例还可以包括在外延层下面的下部外延层，下部外延层包括例如硅碳磷（SiCP）层。

2. 发明授权

US08426265B2 Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
标题翻译：在栅极第一流中在CMOS电路中增长应变诱导材料的方法
公开(公告)号：US08426265B2
公开(公告)日：2013-04-23
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

3. 发明授权

US08421191B2 Monolayer dopant embedded stressor for advanced CMOS 有权
标题翻译：单层掺杂剂嵌入式应力器用于高级CMOS
公开(公告)号：US08421191B2
公开(公告)日：2013-04-16
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L31/117
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

4. 发明申请

US20130009277A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20130009277A1
公开(公告)日：2013-01-10
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

5. 发明授权

US08338279B2 Reduced pattern loading for doped epitaxial process and semiconductor structure 失效
标题翻译：用于掺杂外延工艺和半导体结构的减少图案负载
公开(公告)号：US08338279B2
公开(公告)日：2012-12-25
申请号：US13075450
申请日：2011-03-30
申请人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
发明人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
IPC分类号： H01L21/20
CPC分类号： H01L21/823425 , H01L21/02529 , H01L21/02576 , H01L21/823412 , H01L22/12 , H01L22/34 , H01L29/66636 , H01L29/7848
摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
摘要翻译：提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

6. 发明申请

US20120280251A1 CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS 有权
标题翻译：扩展区域和嵌入式硅 - 碳合金源/排水区之间的无密封接口
公开(公告)号：US20120280251A1
公开(公告)日：2012-11-08
申请号：US13101260
申请日：2011-05-05
申请人： ABHISHEK DUBE , Viorel Ontalus
发明人： ABHISHEK DUBE , Viorel Ontalus
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.
摘要翻译：在硅衬底上形成栅极叠层，并且在栅极堆叠周围形成源极/漏极延伸区域。在栅极堆叠周围形成介电隔离物。通过蚀刻在栅极堆叠和电介质间隔物周围形成一对沟槽，使得源极/漏极延伸区域的侧壁被暴露。在每个沟槽内，通过第一选择性外延工艺将n掺杂硅衬垫沉积在沟槽的侧壁上，以便覆盖介质间隔物与源极/漏极延伸区之间的界面。在每个沟槽内，随后沉积n掺杂的单晶硅 - 碳合金以通过第二选择性外延工艺填充沟槽。 n掺杂单晶硅衬垫和n掺杂单晶硅碳合金的组合用作n型场效应晶体管（NFET）的嵌入式源极/漏极区域，其对该沟道施加拉伸应力晶体管。

7. 发明授权

US08173524B1 Process for epitaxially growing epitaxial material regions 有权
标题翻译：用于外延生长外延材料区的方法
公开(公告)号：US08173524B1
公开(公告)日：2012-05-08
申请号：US13004201
申请日：2011-01-11
申请人： Ashima B. Chakravarti , Anthony I. Chou , Abhishek Dube , Dominic J. Schepis
发明人： Ashima B. Chakravarti , Anthony I. Chou , Abhishek Dube , Dominic J. Schepis
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/165 , H01L21/0237 , H01L21/02529 , H01L21/02639 , H01L29/78 , H01L29/7848
摘要： Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.
摘要翻译：方法通过在硅衬底上形成至少两个栅极叠层并在栅叠层的侧面上形成侧壁间隔来形成外延材料。这种方法在相邻的栅叠层之间的硅衬底中形成凹陷。该方法还在凹槽的底部提供衬垫，并且从凹槽的侧壁外延生长外延材料，以用外延材料填充凹部。

8. 发明申请

US20120043556A1 EPITAXIAL GROWTH OF SILICON DOPED WITH CARBON AND PHOSPHORUS USING HYDROGEN CARRIER GAS 有权
标题翻译：用碳氢化合物与碳氢化合物掺杂的硅的外延生长
公开(公告)号：US20120043556A1
公开(公告)日：2012-02-23
申请号：US12860236
申请日：2010-08-20
申请人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
发明人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
IPC分类号： H01L29/12 , H01L21/203
CPC分类号： H01L21/0262 , H01L21/0237 , H01L21/02529 , H01L21/02576 , H01L21/02587 , H01L21/02636 , H01L29/045 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
摘要翻译：一种用于沉积硅碳外延膜（Si：C）的方法。在一个实施例中，该方法包括：使用由含硅烷的气体前体，含碳气体前体和正极材料构成的沉积气体前体，在半导体沉积表面上沉积n型掺杂硅碳（Si：C）型气体掺杂剂源。沉积气体前体用氢（H 2）载气引入半导体沉积表面。沉积外延膜的方法可以包括由氯化氢（HCl）气体蚀刻剂和氢（H 2）载气提供的蚀刻反应。

9. 发明申请

US20110316046A1 Field Effect Transistor Device 有权
标题翻译：场效应晶体管器件
公开(公告)号：US20110316046A1
公开(公告)日：2011-12-29
申请号：US12825791
申请日：2010-06-29
申请人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
发明人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L21/823412 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78684
摘要： A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.
摘要翻译：一种用于形成场效应晶体管器件的方法，包括：在衬底上形成栅极叠层部分，在栅堆叠部分和衬底的一部分上形成间隔部分，去除衬底的暴露部分，将第一硅材料外延生长衬底的暴露部分，去除外延生长的第一硅材料的一部分以暴露衬底的第二部分，以及在衬底的暴露的第二部分和第一硅材料上外延生长第二硅材料。

10. 发明申请

US20110162875A1 SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION 有权
标题翻译：选择铜包层沉积
公开(公告)号：US20110162875A1
公开(公告)日：2011-07-07
申请号：US12683857
申请日：2010-01-07
申请人： Tien-Jen Cheng , Abhishek Dube , Zhengwen Li , Huilong Zhu
发明人： Tien-Jen Cheng , Abhishek Dube , Zhengwen Li , Huilong Zhu
IPC分类号： H05K1/09 , B05D5/12
CPC分类号： H01L21/76834 , H01L21/76826 , H01L21/76832 , H05K3/282 , H05K3/388 , H05K3/4682
摘要： A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.
摘要翻译：金属互连结构在含铜结构中的铜原子和自对准铜封装层之间提供高粘合强度，其仅选择性地沉积在暴露的铜表面上。下层金属互连结构包括第一介电材料层和嵌入在下金属衬里中的含铜结构。在形成含铜结构的平坦化工艺之后，将含铜结构体的露出表面形成Cu-S键的材料施加到含铜结构体的表面。该材料仅选择性地沉积在暴露的Cu表面上，从而形成自对准的铜封装层，并且对下面的铜表面提供高粘附强度。随后可以在铜封装层上形成电介质盖层和上层金属互连结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式