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    • 7. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF REALIZING REDUCTION IN SIZE
    • 具有实现减小尺寸的半导体集成电路
    • US20080099874A1
    • 2008-05-01
    • US11923132
    • 2007-10-24
    • Hiroshi Kumano
    • Hiroshi Kumano
    • H01L29/00
    • H01L21/76286
    • In a semiconductor integrated circuit in which an element isolating insulation film is provided on a substrate, an isolated Si region in the substrate is a shape composed of straight lines which form four sides and circular arcs which form four corners. Further, the adjacent Si regions share element isolating insulation films, and the adjacent Si regions are separated by one element isolating insulation film. Furthermore, widths of the element isolating insulation films are the same in a chip pattern. When the width of the element isolating insulation film is set to a, and a curvature radius of curved lines at four corners of the Si region is set to r; the width a and the curvature radius r are determined so as to satisfy conditions of r>0.7a in the case where the element isolating insulation films are intersected only in a cross shape, and r>1.5a in the case where the element isolating insulation films include a portion intersected in a T shape.
    • 在基板上设置有元件隔离绝缘膜的半导体集成电路中,基板中的隔离Si区域由形成四个边的直线和形成四个角的圆弧构成。 此外,相邻的Si区域共享元件隔离绝缘膜,并且相邻的Si区域被一个元件隔离绝缘膜隔开。 此外,元件隔离绝缘膜的宽度在芯片图案中是相同的。 当元件隔离绝缘膜的宽度设定为a,将Si区域的四个角部的曲线的曲率半径设定为r时, 在元件隔离绝缘膜仅交叉形状的情况下,宽度a和曲率半径r被确定为满足r> 0.7a的条件,并且在元件隔离绝缘 膜包括以T形交叉的部分。