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1. 发明授权

US07714366B2 CMOS transistor with a polysilicon gate electrode having varying grain size 有权
标题翻译：具有晶体尺寸变化的多晶硅栅电极的CMOS晶体管
公开(公告)号：US07714366B2
公开(公告)日：2010-05-11
申请号：US10904565
申请日：2004-11-16
申请人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
发明人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L21/28035 , H01L29/4925 , H01L29/665
摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.
摘要翻译：通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该第一区域并且远离栅极电介质。多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。

2. 发明授权

US06893948B2 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 失效
标题翻译：通过沉积不同晶粒尺寸的多晶硅来减少多晶硅栅电极中的多晶硅耗尽的方法
公开(公告)号：US06893948B2
公开(公告)日：2005-05-17
申请号：US10616962
申请日：2003-07-11
申请人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
发明人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/20 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L29/4925 , H01L29/665
摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.
摘要翻译：通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一区域并且远离栅极电介质。该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

3. 发明授权

US06670263B2 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 失效
公开(公告)号：US06670263B2
公开(公告)日：2003-12-30
申请号：US09802702
申请日：2001-03-10
申请人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
发明人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
IPC分类号： H01L213205
CPC分类号： H01L21/28035 , H01L29/4925 , H01L29/665
摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

4. 发明授权

US06326275B1 DRAM cell with vertical CMOS transistor 有权
标题翻译：具有垂直CMOS晶体管的DRAM单元
公开(公告)号：US06326275B1
公开(公告)日：2001-12-04
申请号：US09559363
申请日：2000-04-24
申请人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
发明人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.
摘要翻译：具有沟槽电容器的DRAM存储单元包括形成在沟槽顶部的垂直传输晶体管，该工艺在牺牲本征聚间隔层上方的上侧壁上形成掺杂的多晶保护层，掺杂的多晶硅保护侧壁，而本征聚间隔层被去除并被导电带层替代，导电带层都形成来自电容器电极的带，并且用作掺杂剂源以在硅衬底中形成晶体管电极; 保护层和带材的上部被同时移除，使得不需要额外的步骤; 之后，沟槽壁被氧化以形成晶体管栅极电介质并且沉积导电材料以同时形成用于垂直晶体管的字线和栅极。

5. 发明授权

US06258673B1 Multiple thickness of gate oxide 失效
标题翻译：多重厚度的栅极氧化物
公开(公告)号：US06258673B1
公开(公告)日：2001-07-10
申请号：US09470460
申请日：1999-12-22
申请人： Kevin M. Houlihan , Liang-Kai Han , Dale W. Martin
发明人： Kevin M. Houlihan , Liang-Kai Han , Dale W. Martin
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the standard oxide thickness is formed in the first set of active areas, an oxide thickness of greater than the standard oxide thickness is formed in the third set of active areas, and a fourth oxide thickness greater than the third oxide thickness is formed in the fourth set of active areas.
摘要翻译：一种通过以下步骤形成具有四组有源区的四种厚度的栅极氧化物的集成电路的方法：氧化硅衬底以形成具有适合于期望阈值电压晶体管的厚度的初始氧化物; 沉积阻挡掩模以留下暴露的第一和第四组有效区域; 用一定剂量的生长变化的离子注入第一组和第四组活性区域，从而使第一组活性区域或多或少抵抗氧化，同时使第四组活性区域易于加速氧化; 剥离阻挡面具; 形成第二阻挡掩模以使第一和第二组有效区域暴露; 剥离暴露的活性区域中的初始氧化物; 剥离第二阻挡面具; 表面清洗晶圆; 以及在第二氧化步骤中氧化所述衬底，使得在所述第二组有源区中形成标准氧化物厚度，由此在所述第一组有源区中形成大于或小于标准氧化物厚度的氧化物厚度，在第三组有源区中形成大于标准氧化物厚度的厚度，并且在第四组有源区中形成大于第三氧化物厚度的第四氧化物厚度。

6. 发明授权

US06342431B2 Method for eliminating transfer gate sacrificial oxide 失效
标题翻译：消除传输门牺牲氧化物的方法
公开(公告)号：US06342431B2
公开(公告)日：2002-01-29
申请号：US09173089
申请日：1998-10-14
申请人： Kevin M. Houlihan , Jed H. Rankin
发明人： Kevin M. Houlihan , Jed H. Rankin
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/28167 , H01L21/3143 , H01L21/31612 , H01L21/823878 , H01L21/823892
摘要： A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成氧化物层，在氧化物层上形成氮化硅层，使用氧化物层和氮化物层在衬底中形成隔离区域，去除氮化硅层，使用原始氧化物层作为屏幕的离子注入掺杂剂离子进入衬底，并且去除氧化物层并在衬底上形成栅极氧化物层。形成半导体器件的有源区域的另一种方法包括使用衬垫氧化物，在除去氧化物/膜掩模叠层之上的膜层之后留下用于在衬底中形成的阱注入的屏蔽层，去除氧化物层和在不使用牺牲氧化物的情况下，在定义井注入之后，在衬底上形成栅极氧化物。

7. 发明授权

US06504207B1 Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same 失效
标题翻译：创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法，以及与之相同的操作条件
公开(公告)号：US06504207B1
公开(公告)日：2003-01-07
申请号：US09609292
申请日：2000-06-30
申请人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
发明人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , G11C16/0408 , H01L29/42328
摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
摘要翻译：与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。在编程期间，在浮栅和程序门之间发生电子隧穿。

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