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1. 发明授权

US07132338B2 Methods to fabricate MOSFET devices using selective deposition process 有权
标题翻译：使用选择性沉积工艺制造MOSFET器件的方法
公开(公告)号：US07132338B2
公开(公告)日：2006-11-07
申请号：US10845984
申请日：2004-05-14
申请人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
发明人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/28044 , H01L21/28114 , H01L21/823807 , H01L29/165 , H01L29/66242 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7848
摘要： In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more. The method further provides depositing on the first silicon-containing layer a second silicon-containing layer wherein a second germanium concentration of about 15 at % or less, exposing the substrate surface to air to form a native oxide layer, removing the native oxide layer to expose the second silicon-containing layer, and depositing a third silicon-containing layer on the second silicon-containing layer. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing epitaxially a first silicon-containing layer on the substrate surface with a first lattice strain, and depositing epitaxially on the first silicon-containing layer a second silicon-containing layer with a second lattice strain greater than the first lattice strain.
摘要翻译：在一个实施例中，提供了一种在衬底表面上制造硅基器件的方法，其包括通过将衬底表面暴露于包含Cl 2 SiH 2的第一工艺气体来沉积第一含硅层，锗源，第一蚀刻剂和载气，并且通过将第一含硅层暴露于包含SiH 4 N 2的第二工艺气体而沉积第二含硅层，和第二蚀刻剂。在另一个实施例中，提供了一种用于在衬底表面上沉积含硅材料的方法，其包括以约15at％或更多的第一锗浓度在衬底表面上沉积第一含硅层。该方法进一步提供了在第一含硅层上沉积第二含硅层，其中第二锗浓度为约15原子％或更低，将基底表面暴露于空气中以形成天然氧化物层，将天然氧化物层去除暴露第二含硅层，并在第二含硅层上沉积第三含硅层。在另一个实施例中，提供了一种用于在衬底表面上沉积含硅材料的方法，其包括以第一晶格应变在衬底表面上外延沉积第一含硅层，并且在第一含硅层上外延沉积第二含硅层具有大于第一晶格应变的第二晶格应变。

2. 发明授权

US07737007B2 Methods to fabricate MOSFET devices using a selective deposition process 有权
标题翻译：使用选择性沉积工艺制造MOSFET器件的方法
公开(公告)号：US07737007B2
公开(公告)日：2010-06-15
申请号：US12201681
申请日：2008-08-29
申请人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
发明人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
IPC分类号： H01L21/20
CPC分类号： H01L21/0237 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L29/78 , H01L29/7848
摘要： In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
摘要翻译：在一个实施例中，提供了一种在处理室内具有电介质材料和源极/漏极区域的衬底上形成硅基材料的方法，其包括将衬底暴露于包含硅烷，甲基硅烷，第一蚀刻剂的第一工艺气体，和氢气以在其上沉积第一含硅层。第一含硅层可以选择性地沉积在衬底的源极/漏极区上，同时第一含硅层可被蚀刻掉在衬底的电介质材料的表面上。随后，该方法进一步提供将衬底暴露于包含二氯硅烷和第二蚀刻剂的第二工艺气体，以在衬底上的第一含硅层的表面上选择性地沉积第二含硅层。

3. 发明授权

US07439142B2 Methods to fabricate MOSFET devices using a selective deposition process 有权
标题翻译：使用选择性沉积工艺制造MOSFET器件的方法
公开(公告)号：US07439142B2
公开(公告)日：2008-10-21
申请号：US11539775
申请日：2006-10-09
申请人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
发明人： Arkadii V. Samoilov , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/28044 , H01L21/28114 , H01L21/823807 , H01L29/165 , H01L29/66242 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7848
摘要： In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
摘要翻译：在一个实施例中，提供了一种在处理室内具有电介质材料和源极/漏极区域的衬底上形成硅基材料的方法，其包括将衬底暴露于包含硅烷，甲基硅烷，第一蚀刻剂的第一工艺气体，和氢气以在其上沉积第一含硅层。第一含硅层可以被选择性地沉积在衬底的源极/漏极区上，同时第一含硅层可被蚀刻掉在衬底的电介质材料的表面上。随后，该方法进一步提供将衬底暴露于包含二氯硅烷和第二蚀刻剂的第二工艺气体，以在衬底上的第一含硅层的表面上选择性地沉积第二含硅层。

4. 发明申请

US20090011578A1 METHODS TO FABRICATE MOSFET DEVICES USING A SELECTIVE DEPOSITION PROCESS 有权
标题翻译：使用选择性沉积工艺制作MOSFET器件的方法
公开(公告)号：US20090011578A1
公开(公告)日：2009-01-08
申请号：US12201681
申请日：2008-08-29
申请人： ARKADII V. SAMOILOV , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
发明人： ARKADII V. SAMOILOV , Yihwan Kim , Errol Sanchez , Nicholas C. Dalida
IPC分类号： H01L21/203
CPC分类号： H01L21/0237 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L29/78 , H01L29/7848
摘要： In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
摘要翻译：在一个实施例中，提供了一种在处理室内具有电介质材料和源极/漏极区的衬底上形成硅基材料的方法，其包括将衬底暴露于包含硅烷，甲基硅烷，第一蚀刻剂的第一工艺气体，和氢气以在其上沉积第一含硅层。第一含硅层可以选择性地沉积在衬底的源极/漏极区上，同时第一含硅层可被蚀刻掉在衬底的电介质材料的表面上。随后，该方法进一步提供将衬底暴露于包含二氯硅烷和第二蚀刻剂的第二工艺气体，以在衬底上的第一含硅层的表面上选择性地沉积第二含硅层。

5. 发明申请

US20070082451A1 METHODS TO FABRICATE MOSFET DEVICES USING A SELECTIVE DEPOSITION PROCESS 有权
标题翻译：使用选择性沉积工艺制作MOSFET器件的方法
公开(公告)号：US20070082451A1
公开(公告)日：2007-04-12
申请号：US11539775
申请日：2006-10-09
申请人： ARKADII SAMOILOV , Yihwan Kim , Errol Sanchez , Nicholas Dalida
发明人： ARKADII SAMOILOV , Yihwan Kim , Errol Sanchez , Nicholas Dalida
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/28044 , H01L21/28114 , H01L21/823807 , H01L29/165 , H01L29/66242 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7848
摘要： In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
摘要翻译：在一个实施例中，提供了一种在处理室内具有电介质材料和源极/漏极区域的衬底上形成硅基材料的方法，其包括将衬底暴露于包含硅烷，甲基硅烷，第一蚀刻剂的第一工艺气体，和氢气以在其上沉积第一含硅层。第一含硅层可以选择性地沉积在衬底的源极/漏极区上，同时第一含硅层可被蚀刻掉在衬底的电介质材料的表面上。随后，该方法进一步提供将衬底暴露于包含二氯硅烷和第二蚀刻剂的第二工艺气体，以在衬底上的第一含硅层的表面上选择性地沉积第二含硅层。

6. 发明授权

US07732269B2 Method of ultra-shallow junction formation using Si film alloyed with carbon 有权
标题翻译：使用与碳合金化的Si膜的超浅结结形成方法
公开(公告)号：US07732269B2
公开(公告)日：2010-06-08
申请号：US11742932
申请日：2007-05-01
申请人： Yihwan Kim , Majeed A. Foad , Yonah Cho , Zhiyuan Ye , Ali Zojaji , Errol Sanchez
发明人： Yihwan Kim , Majeed A. Foad , Yonah Cho , Zhiyuan Ye , Ali Zojaji , Errol Sanchez
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02664 , H01L21/2233 , H01L21/26513 , H01L29/165 , H01L29/66287 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A method for forming an ultra shallow junction on a substrate is provided. In certain embodiments a method of forming an ultra shallow junction on a substrate is provided. The substrate is placed into a process chamber. A silicon carbon layer is deposited on the substrate. The silicon carbon layer is exposed to a dopant. The substrate is heated to a temperature greater than 950° C. so as to cause substantial annealing of the dopant within the silicon carbon layer. In certain embodiments the substrate is heated to a temperature between about 1000° C. and about 1100°. In certain embodiments the substrate is heated to a temperature between about 1030° C. and 1050° C. In certain embodiments, a structure having an abrupt p-n junction is provided.
摘要翻译：提供了一种在基板上形成超浅结的方法。在某些实施例中，提供了在衬底上形成超浅结的方法。将基底放置在处理室中。硅基层沉积在基底上。硅碳层暴露于掺杂剂。将基板加热至大于950℃的温度，以使硅碳层内的掺杂剂发生实际退火。在某些实施方案中，将基材加热至约1000℃至约1100℃之间的温度。在某些实施方案中，将衬底加热至约1030℃至1050℃之间的温度。在某些实施方案中，提供具有突变p-n结的结构。

7. 发明授权

US09058988B2 Methods for depositing layers having reduced interfacial contamination 有权
标题翻译：沉积界面污染减少的方法
公开(公告)号：US09058988B2
公开(公告)日：2015-06-16
申请号：US12717266
申请日：2010-03-04
申请人： Jean R. Vatus , Jinsong Tang , Yihwan Kim , Satheesh Kuppurao , Errol Sanchez
发明人： Jean R. Vatus , Jinsong Tang , Yihwan Kim , Satheesh Kuppurao , Errol Sanchez
IPC分类号： H01L21/00 , H01L21/02 , C23C16/02 , C23C16/24
CPC分类号： H01L21/02538 , C23C16/0245 , C23C16/24 , H01L21/02381 , H01L21/02532 , H01L21/02661
摘要： Methods of depositing layers having reduced interfacial contamination are disclosed herein. The inventive methods may advantageously reduce contamination at the interface between deposited layers, for example, between a deposited layer and an underlying substrate or film. In some embodiments, a method of depositing a layer may include annealing a silicon-containing layer having a first layer disposed thereon in a reducing atmosphere; removing the first layer using an etching process to expose the silicon-containing layer after annealing; and depositing a second layer on the exposed silicon-containing layer.
摘要翻译：本文公开了沉积具有减小的界面污染的层的方法。本发明的方法可以有利地减少沉积层之间的界面处的污染，例如沉积层和下面的基底或膜之间的污染。在一些实施例中，沉积层的方法可以包括在还原气氛中退火其上设置有第一层的含硅层; 使用蚀刻工艺除去第一层，以在退火后露出含硅层; 以及在暴露的含硅层上沉积第二层。

8. 发明申请

US20070256627A1 METHOD OF ULTRA-SHALLOW JUNCTION FORMATION USING SI FILM ALLOYED WITH CARBON 有权
标题翻译：使用与碳合金制成的超薄结块形成方法
公开(公告)号：US20070256627A1
公开(公告)日：2007-11-08
申请号：US11742932
申请日：2007-05-01
申请人： YIHWAN KIM , Majeed Foad , Yonah Cho , Zhiyuan Ye , Ali Zojaji , Errol Sanchez
发明人： YIHWAN KIM , Majeed Foad , Yonah Cho , Zhiyuan Ye , Ali Zojaji , Errol Sanchez
IPC分类号： C30B23/00 , C23C16/00 , B05D3/02 , C30B25/00
CPC分类号： H01L29/7848 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02664 , H01L21/2233 , H01L21/26513 , H01L29/165 , H01L29/66287 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A method for forming an ultra shallow junction on a substrate is provided. In certain embodiments a method of forming an ultra shallow junction on a substrate is provided. The substrate is placed into a process chamber. A silicon carbon layer is deposited on the substrate. The silicon carbon layer is exposed to a dopant. The substrate is heated to a temperature greater than 950° C. so as to cause substantial annealing of the dopant within the silicon carbon layer. In certain embodiments the substrate is heated to a temperature between about 1000° C. and about 1100°. In certain embodiments the substrate is heated to a temperature between about 1030° C. and 1050° C. In certain embodiments, a structure having an abrupt p-n junction is provided.
摘要翻译：提供了一种在基板上形成超浅结的方法。在某些实施例中，提供了在衬底上形成超浅结的方法。将基底放置在处理室中。硅基层沉积在基底上。硅碳层暴露于掺杂剂。将基板加热至大于950℃的温度，以使硅碳层内的掺杂剂发生实际退火。在某些实施方案中，将基材加热至约1000℃至约1100℃之间的温度。在某些实施方案中，将衬底加热至约1030℃至1050℃之间的温度。在某些实施方案中，提供具有突变p-n结的结构。

9. 发明申请

US20050079692A1 Methods to fabricate MOSFET devices using selective deposition process 有权
标题翻译：使用选择性沉积工艺制造MOSFET器件的方法
公开(公告)号：US20050079692A1
公开(公告)日：2005-04-14
申请号：US10845984
申请日：2004-05-14
申请人： Arkadii Samoilov , Yihwan Kim , Errol Sanchez , Nicholas Dalida
发明人： Arkadii Samoilov , Yihwan Kim , Errol Sanchez , Nicholas Dalida
IPC分类号： H01L21/20 , H01L21/205 , H01L21/28 , H01L21/331 , H01L21/336 , H01L21/8238 , H01L21/36
CPC分类号： H01L21/823814 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/28044 , H01L21/28114 , H01L21/823807 , H01L29/165 , H01L29/66242 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7848
摘要： In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more. The method further provides depositing on the first silicon-containing layer a second silicon-containing layer wherein a second germanium concentration of about 15 at % or less, exposing the substrate surface to air to form a native oxide layer, removing the native oxide layer to expose the second silicon-containing layer, and depositing a third silicon-containing layer on the second silicon-containing layer. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing epitaxially a first silicon-containing layer on the substrate surface with a first lattice strain, and depositing epitaxially on the first silicon-containing layer a second silicon-containing layer with a second lattice strain greater than the first lattice strain.
摘要翻译：在一个实施例中，提供了一种在衬底表面上制造硅基器件的方法，其包括通过将衬底表面暴露于包括Cl 2 SiH 2，锗源，第一蚀刻剂和第二蚀刻剂的第一工艺气体来沉积第一含硅层载气并通过将第一含硅层暴露于包含SiH 4和第二蚀刻剂的第二工艺气体而沉积第二含硅层。在另一个实施例中，提供了一种用于在衬底表面上沉积含硅材料的方法，其包括以约15at％或更多的第一锗浓度在衬底表面上沉积第一含硅层。该方法进一步提供了在第一含硅层上沉积第二含硅层，其中第二锗浓度为约15原子％或更低，将基底表面暴露于空气中以形成天然氧化物层，将天然氧化物层去除暴露第二含硅层，并在第二含硅层上沉积第三含硅层。在另一个实施例中，提供了一种用于在衬底表面上沉积含硅材料的方法，其包括以第一晶格应变在衬底表面上外延沉积第一含硅层，并且在第一含硅层上外延沉积第二含硅层具有大于第一晶格应变的第二晶格应变。

10. 发明授权

US08991332B2 Apparatus to control semiconductor film deposition characteristics 有权
标题翻译：控制半导体膜沉积特性的装置
公开(公告)号：US08991332B2
公开(公告)日：2015-03-31
申请号：US12394203
申请日：2009-02-27
申请人： Satheesh Kuppurao , David K. Carlson , Manish Hemkar , Andrew Lam , Errol Sanchez , Howard Beckford
发明人： Satheesh Kuppurao , David K. Carlson , Manish Hemkar , Andrew Lam , Errol Sanchez , Howard Beckford
IPC分类号： C23C16/46 , C23C16/52 , C23C16/44 , H01L21/67
CPC分类号： C23C16/46 , C23C16/4411 , C23C16/52 , H01L21/67115 , H01L21/67248
摘要： Systems and apparatus are disclosed for adjusting the temperature of at least a portion of the surface of a reaction chamber during a film formation process to control film properties. More than one portion of the chamber surface may be temperature-modulated.
摘要翻译：公开了用于在成膜过程中调节反应室表面的至少一部分的温度以控制膜性质的系统和装置。腔表面的多于一个部分可以进行温度调制。

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