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1. 发明授权

US06538522B1 Method and ring oscillator for evaluating dynamic circuits 有权
标题翻译：用于评估动态电路的方法和环形振荡器
公开(公告)号：US06538522B1
公开(公告)日：2003-03-25
申请号：US09977423
申请日：2001-10-15
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
IPC分类号： H03B2700
CPC分类号： H03K3/0315
摘要： Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit. The multiplexer receives the pulse output of the one-shot pulse generator and includes a select input for selecting the output of the dynamic circuit to be evaluated or the pulse output of the one-shot pulse generator. By inserting the evaluation circuit into a path that can be multiplexed in and out of the oscillator path, and by measuring the difference between the frequency with and without the evaluation circuit in the path, the performance of the evaluation circuit can be accurately determined.
摘要翻译：提供测量方法和环形振荡器电路用于评估动态电路。环形振荡器电路包括接收单个转换输入信号的单触发脉冲发生器，并产生具有上升的转换和下降转换的脉冲输出信号。要评估的动态电路耦合到接收单触发脉冲发生器的脉冲输出信号的单触发脉冲发生器的输出，并在输出端产生延迟的输出脉冲。二分之一电路耦合到待评估的动态电路的输出。二分之一电路的输出信号反馈给单触发脉冲发生器，重复循环，从而振荡。多路复用器连接在待评估的动态电路的输出端与分频电路之间。复用器接收单触发脉冲发生器的脉冲输出，并且包括用于选择要评估的动态电路的输出或单触发脉冲发生器的脉冲输出的选择输入。通过将评估电路插入到可以复用在振荡器路径中的路径之外，并且通过测量路径中具有和不具有评估电路的频率之间的差异，可以准确地确定评估电路的性能。

2. 发明授权

US5778243A Multi-threaded cell for a memory 失效
标题翻译：用于内存的多线程单元
公开(公告)号：US5778243A
公开(公告)日：1998-07-07
申请号：US675315
申请日：1996-07-03
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
IPC分类号： G06F12/00 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G11C8/16 , G06F12/02 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/3851 , G11C8/16
摘要： A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.
摘要翻译：一种用于多线程计算机系统中的多线程存储器（和相关方法），其中多个线程与单个处理器一起使用。多线程内存包括：多线程存储单元; 至少一个写入解码器，向所选择的多线程存储单元提供信息; 以及至少一个读取解码器从所选择的多线程存储单元访问信息。每个多线程存储单元包括：N个存储元件，其中N≥2，N个存储元件中的每一个具有线程通信内容; 写入接口，向所述小区内存储元件提供信息; 以及从单元内存储元件读取信息的读取接口。至少一个小区内读取和写入接口至少部分地通过识别对应的线程来选择线程对应内容之一，以实现小区内线程通信的内容选择。

3. 发明授权

US06668358B2 Dual threshold gate array or standard cell power saving library circuits 失效
标题翻译：双阈值门阵列或标准单元省电库电路
公开(公告)号：US06668358B2
公开(公告)日：2003-12-23
申请号：US09968376
申请日：2001-10-01
申请人： David Michael Friend , Nghia Van Phan , Byron D. Scott , Daniel Lawrence Stasiak , Bradley Craig White
发明人： David Michael Friend , Nghia Van Phan , Byron D. Scott , Daniel Lawrence Stasiak , Bradley Craig White
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.
摘要翻译：公开了一种方法，其中通过ASIC库中的功能等效的逻辑块检查ASIC模拟逻辑芯片上的逻辑块的子集以供替换。功能上等效的逻辑块替换被设计为平均显示出明显较少的亚阈值漏电流。替换块是执行速度较慢的块，因此进行检查以确保不违反时序要求。

4. 发明授权

US06909159B2 Method and apparatus to make a semiconductor chip susceptible to radiation failure 有权
标题翻译：使半导体芯片易受辐射破坏的方法和装置
公开(公告)号：US06909159B2
公开(公告)日：2005-06-21
申请号：US10176233
申请日：2002-06-20
申请人： David Michael Friend , Nghia Van Phan , Michael James Rohn
发明人： David Michael Friend , Nghia Van Phan , Michael James Rohn
IPC分类号： G11C11/412 , H01L21/762 , H01L27/12 , H03K19/173 , G11C5/00
CPC分类号： H03K19/1731 , G11C11/4125 , H01L21/76243 , H01L27/1203
摘要： Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.
摘要翻译：提供了用于降低半导体芯片的整体辐射硬度的方法和装置。提供了辐射检测器和故障存储器。故障存储器产生禁用信号或信号。禁用信号是用户逻辑功能的必需输入，例如片外驱动器，芯片外接收器，时钟或静态随机存取存储器。当辐射检测器检测到辐射时，该检测被存储在故障存储器中。禁用信号在有效时会导致部分或全部用户功能不起作用。当半导体芯片在绝缘体上绝缘体（SOI）互补金属氧化物半导体（CMOS）工艺制造时，本发明是特别重要的，其是自然辐射的。

5. 发明授权

US06990510B2 Wide adder with critical path of three gates 失效
公开(公告)号：US06990510B2
公开(公告)日：2006-01-24
申请号：US10054065
申请日：2002-01-22
申请人： David Michael Friend , David Arnold Luick , Nghia Van Phan
发明人： David Michael Friend , David Arnold Luick , Nghia Van Phan
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/3872
摘要： Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

6. 发明授权

US07420832B1 Array split across three-dimensional interconnected chips 有权
标题翻译：阵列分裂穿过三维互连芯片
公开(公告)号：US07420832B1
公开(公告)日：2008-09-02
申请号：US11741902
申请日：2007-04-30
申请人： Eric John Lukes , Nghia Van Phan
发明人： Eric John Lukes , Nghia Van Phan
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C7/12 , G11C7/18 , G11C8/14
摘要： A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
摘要翻译：半导体存储阵列在电路的第一平面上具有第一阵列部分，在电路的第二平面上具有第二阵列部分。复合位线和/或复合字线被分割并布置成具有第一阵列部分上的第一部分和第二阵列部分上的第二部分。复合字线或复合位线的两个部分在电路的不同平面上，并且三维互连连接字线部分的近端或位线部分的近端。字线驱动器并行驱动字线部分。位线驱动器并行驱动位线部分。复合字或位线下的信号传播时间显着小于对应的未分割字或位线的信号传播时间。

7. 发明授权

US07118274B2 Method and reference circuit for bias current switching for implementing an integrated temperature sensor 失效
标题翻译：用于实现集成温度传感器的偏置电流开关的方法和参考电路
公开(公告)号：US07118274B2
公开(公告)日：2006-10-10
申请号：US10849580
申请日：2004-05-20
申请人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
发明人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
IPC分类号： G01K7/01 , G01K7/14 , G05F3/24 , G05F3/26
CPC分类号： G01K7/01
摘要： A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.
摘要翻译：提供了用于实现集成温度传感器的偏置电流切换的方法和参考电路。产生第一偏置电流并且恒定地施加到热感测二极管。通过选择性地将乘法电流从电流乘法器切换到热感测二极管或负载二极管，来向热感测二极管提供第二偏置电流。参考电路包括耦合到电流镜的参考电流源。电流镜向热敏二极管提供第一偏置电流。电流镜耦合到提供倍增电流的电流倍增器。到热敏二极管的第二偏置电流包括第一偏置电流和来自当前乘法器的相乘电流。通过选择性地切换热感测二极管和虚拟负载二极管之间的倍增电流来提供到热敏二极管的第二偏置电流。

8. 发明授权

US5812521A Static adder using BICMOS emitter dot circuits 失效
标题翻译：使用BICMOS发射极点电路的静态加法器
公开(公告)号：US5812521A
公开(公告)日：1998-09-22
申请号：US674098
申请日：1996-07-01
申请人： Sheldon Bernard Levenstein , Nghia Van Phan
发明人： Sheldon Bernard Levenstein , Nghia Van Phan
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508
摘要： A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plurality of half-sum signals for each of the pairs of same-order bits. The summing circuit adds a corresponding half-sum signal to a carry signal from a preceding lower order summing circuit. The carry look-ahead circuit generates a carry signal for higher order summing circuits. Each of the carry look-ahead circuits includes a plurality of logic arrays, each comprising one or more field effect devices coupled in parallel between a first node and a second node, where each of the field effect devices has a gate input to receive lower order addend and augend bits in accordance with a predetermined carry look-ahead equation. The carry look-ahead logic further includes a plurality of bipolar devices, coupled in parallel between a supply voltage and an output node, where each has a base terminal coupled to one of the first nodes of the plurality of field effect devices to provide a sum term of the predetermined sum-of-products at the output node.
摘要翻译：一个用于加上两个n位操作数的并行静态加法器，加法器包括半和电路，求和电路和进位查找电路。半和电路从两个n位操作数接收一对相同次序的位，并且为每一对相同位数生成多个半和信号。加法电路将相应的半和信号加到来自前一个低阶求和电路的进位信号。进位预先电路为较高阶求和电路产生进位信号。每个进位先行电路包括多个逻辑阵列，每个逻辑阵列包括在第一节点和第二节点之间并联耦合的一个或多个场效应装置，其中每个场效应装置具有用于接收较低阶的门输入根据预定的携带查找方程来加数和加数位。携带预读逻辑还包括多个双极器件，并联耦合在电源电压和输出节点之间，其中每个都具有耦合到多个场效应器件中的第一个节点之一的基极以提供总和在输出节点处的预定总和乘积的项。

9. 发明授权

US5355030A Low voltage BICMOS logic switching circuit 失效
标题翻译：低电压BICMOS逻辑开关电路
公开(公告)号：US5355030A
公开(公告)日：1994-10-11
申请号：US985990
申请日：1992-12-04
申请人： Timothy C. Buchholtz , Nghia Van Phan , Michael J. Rohn
发明人： Timothy C. Buchholtz , Nghia Van Phan , Michael J. Rohn
IPC分类号： H03K19/01 , H03K19/017 , H03K19/08 , H03K19/0944 , H03K19/082 , H03K19/0948
CPC分类号： H03K19/09448 , H03K19/01721
摘要： The present invention involves a BICMOS logic switching circuit biased between upper and lower supply voltages. This circuit includes a CMOS logic circuit driven by a plurality of logic input signals. This logic switching circuit also has a driving circuit coupled to the CMOS logic switching circuit and includes an output node, a first bipolar transistor, and a second bipolar transistor. The first bipolar transistor is coupled in series with the second bipolar transistor with the output node therebetween for providing an output signal on the output node, wherein the second bipolar transistor has a base directly coupled to a field effect transistor switch coupled to the upper supply voltage. The field effect transistor switch is controlled by logic input signals. The circuit also includes a switching circuit coupled to the upper supply voltage, the lower supply voltage, and the output node for causing the output signal on the output node to swing fully between the upper and the lower supply voltages in response to changes in the logic input signals.
摘要翻译：本发明涉及一种偏置在上下电源电压之间的BICMOS逻辑开关电路。该电路包括由多个逻辑输入信号驱动的CMOS逻辑电路。该逻辑开关电路还具有耦合到CMOS逻辑开关电路的驱动电路，并且包括输出节点，第一双极晶体管和第二双极晶体管。第一双极晶体管与第二双极晶体管串联耦合，其间具有输出节点，用于在输出节点上提供输出信号，其中第二双极晶体管具有直接耦合到耦合到较高电源电压的场效应晶体管开关的基极。场效应晶体管开关由逻辑输入信号控制。电路还包括耦合到上电源电压，较低电源电压和输出节点的开关电路，用于使得输出节点上的输出信号响应于逻辑上的变化而在上电源电压和下电源电压之间完全摆动输入信号。

10. 发明申请

US20080266925A1 Array Split Across Three-Dimensional Interconnected Chips 审中-公开
标题翻译：跨三维互连芯片的阵列分割
公开(公告)号：US20080266925A1
公开(公告)日：2008-10-30
申请号：US11869802
申请日：2007-10-10
申请人： Eric John Lukes , Nghia Van Phan
发明人： Eric John Lukes , Nghia Van Phan
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/063 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/14
摘要： A design structure including a semiconductor storage array having a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
摘要翻译：一种设计结构，包括半导体存储阵列，其具有在电路的第一平面上的第一阵列部分和在电路的第二平面上的第二阵列部分。复合位线和/或复合字线被分割并布置成具有第一阵列部分上的第一部分和第二阵列部分上的第二部分。复合字线或复合位线的两个部分在电路的不同平面上，并且三维互连连接字线部分的近端或位线部分的近端。字线驱动器并行驱动字线部分。位线驱动器并行驱动位线部分。复合字或位线下的信号传播时间显着小于对应的未分割字或位线的信号传播时间。

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