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1. 发明授权

US06668358B2 Dual threshold gate array or standard cell power saving library circuits 失效
标题翻译：双阈值门阵列或标准单元省电库电路
公开(公告)号：US06668358B2
公开(公告)日：2003-12-23
申请号：US09968376
申请日：2001-10-01
申请人： David Michael Friend , Nghia Van Phan , Byron D. Scott , Daniel Lawrence Stasiak , Bradley Craig White
发明人： David Michael Friend , Nghia Van Phan , Byron D. Scott , Daniel Lawrence Stasiak , Bradley Craig White
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.
摘要翻译：公开了一种方法，其中通过ASIC库中的功能等效的逻辑块检查ASIC模拟逻辑芯片上的逻辑块的子集以供替换。功能上等效的逻辑块替换被设计为平均显示出明显较少的亚阈值漏电流。替换块是执行速度较慢的块，因此进行检查以确保不违反时序要求。

2. 发明授权

US06538522B1 Method and ring oscillator for evaluating dynamic circuits 有权
标题翻译：用于评估动态电路的方法和环形振荡器
公开(公告)号：US06538522B1
公开(公告)日：2003-03-25
申请号：US09977423
申请日：2001-10-15
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
IPC分类号： H03B2700
CPC分类号： H03K3/0315
摘要： Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit. The multiplexer receives the pulse output of the one-shot pulse generator and includes a select input for selecting the output of the dynamic circuit to be evaluated or the pulse output of the one-shot pulse generator. By inserting the evaluation circuit into a path that can be multiplexed in and out of the oscillator path, and by measuring the difference between the frequency with and without the evaluation circuit in the path, the performance of the evaluation circuit can be accurately determined.
摘要翻译：提供测量方法和环形振荡器电路用于评估动态电路。环形振荡器电路包括接收单个转换输入信号的单触发脉冲发生器，并产生具有上升的转换和下降转换的脉冲输出信号。要评估的动态电路耦合到接收单触发脉冲发生器的脉冲输出信号的单触发脉冲发生器的输出，并在输出端产生延迟的输出脉冲。二分之一电路耦合到待评估的动态电路的输出。二分之一电路的输出信号反馈给单触发脉冲发生器，重复循环，从而振荡。多路复用器连接在待评估的动态电路的输出端与分频电路之间。复用器接收单触发脉冲发生器的脉冲输出，并且包括用于选择要评估的动态电路的输出或单触发脉冲发生器的脉冲输出的选择输入。通过将评估电路插入到可以复用在振荡器路径中的路径之外，并且通过测量路径中具有和不具有评估电路的频率之间的差异，可以准确地确定评估电路的性能。

3. 发明授权

US06909159B2 Method and apparatus to make a semiconductor chip susceptible to radiation failure 有权
标题翻译：使半导体芯片易受辐射破坏的方法和装置
公开(公告)号：US06909159B2
公开(公告)日：2005-06-21
申请号：US10176233
申请日：2002-06-20
申请人： David Michael Friend , Nghia Van Phan , Michael James Rohn
发明人： David Michael Friend , Nghia Van Phan , Michael James Rohn
IPC分类号： G11C11/412 , H01L21/762 , H01L27/12 , H03K19/173 , G11C5/00
CPC分类号： H03K19/1731 , G11C11/4125 , H01L21/76243 , H01L27/1203
摘要： Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.
摘要翻译：提供了用于降低半导体芯片的整体辐射硬度的方法和装置。提供了辐射检测器和故障存储器。故障存储器产生禁用信号或信号。禁用信号是用户逻辑功能的必需输入，例如片外驱动器，芯片外接收器，时钟或静态随机存取存储器。当辐射检测器检测到辐射时，该检测被存储在故障存储器中。禁用信号在有效时会导致部分或全部用户功能不起作用。当半导体芯片在绝缘体上绝缘体（SOI）互补金属氧化物半导体（CMOS）工艺制造时，本发明是特别重要的，其是自然辐射的。

4. 发明授权

US06990510B2 Wide adder with critical path of three gates 失效
公开(公告)号：US06990510B2
公开(公告)日：2006-01-24
申请号：US10054065
申请日：2002-01-22
申请人： David Michael Friend , David Arnold Luick , Nghia Van Phan
发明人： David Michael Friend , David Arnold Luick , Nghia Van Phan
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/3872
摘要： Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

5. 发明授权

US08373486B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08373486B2
公开(公告)日：2013-02-12
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

6. 发明授权

US08686782B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08686782B2
公开(公告)日：2014-04-01
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

7. 发明申请

US20120187987A1 STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：频率自适应电平变换电路的结构
公开(公告)号：US20120187987A1
公开(公告)日：2012-07-26
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L7/08 , H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

8. 发明申请

US20120133413A1 DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：一种频率自适应电平变换电路的设计结构
公开(公告)号：US20120133413A1
公开(公告)日：2012-05-31
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

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