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1. 发明授权

US07420832B1 Array split across three-dimensional interconnected chips 有权
标题翻译：阵列分裂穿过三维互连芯片
公开(公告)号：US07420832B1
公开(公告)日：2008-09-02
申请号：US11741902
申请日：2007-04-30
申请人： Eric John Lukes , Nghia Van Phan
发明人： Eric John Lukes , Nghia Van Phan
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C7/12 , G11C7/18 , G11C8/14
摘要： A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
摘要翻译：半导体存储阵列在电路的第一平面上具有第一阵列部分，在电路的第二平面上具有第二阵列部分。复合位线和/或复合字线被分割并布置成具有第一阵列部分上的第一部分和第二阵列部分上的第二部分。复合字线或复合位线的两个部分在电路的不同平面上，并且三维互连连接字线部分的近端或位线部分的近端。字线驱动器并行驱动字线部分。位线驱动器并行驱动位线部分。复合字或位线下的信号传播时间显着小于对应的未分割字或位线的信号传播时间。

2. 发明申请

US20080266925A1 Array Split Across Three-Dimensional Interconnected Chips 审中-公开
标题翻译：跨三维互连芯片的阵列分割
公开(公告)号：US20080266925A1
公开(公告)日：2008-10-30
申请号：US11869802
申请日：2007-10-10
申请人： Eric John Lukes , Nghia Van Phan
发明人： Eric John Lukes , Nghia Van Phan
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/063 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/14
摘要： A design structure including a semiconductor storage array having a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
摘要翻译：一种设计结构，包括半导体存储阵列，其具有在电路的第一平面上的第一阵列部分和在电路的第二平面上的第二阵列部分。复合位线和/或复合字线被分割并布置成具有第一阵列部分上的第一部分和第二阵列部分上的第二部分。复合字线或复合位线的两个部分在电路的不同平面上，并且三维互连连接字线部分的近端或位线部分的近端。字线驱动器并行驱动字线部分。位线驱动器并行驱动位线部分。复合字或位线下的信号传播时间显着小于对应的未分割字或位线的信号传播时间。

3. 发明授权

US07760843B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07760843B2
公开(公告)日：2010-07-20
申请号：US12187517
申请日：2008-08-07
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

4. 发明授权

US5903195A Automatically ranging phase locked loop circuit for microprocessor clock generation 失效
标题翻译：自动测距锁相环电路，用于微处理器时钟产生
公开(公告)号：US5903195A
公开(公告)日：1999-05-11
申请号：US16848
申请日：1998-01-30
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03L7/095 , H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/10 , Y10S331/02
摘要： An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control. A control signal is applied to the voltage to current converter for selectively controlling an operational mode of the voltage to current converter from a squelched operational mode to an unsquelched operational mode after a set time period. This control signal also is applied to the range control, so that the range control stops changing ranges.
摘要翻译：提供改进的锁相环（PLL）电路用于微处理器时钟产生。环形振荡器提供输出频率信号。电压 - 电流转换器将差分控制电压转换为施加到环形振荡器的可变参考电流。范围控制参考电流发生器将范围控制参考电流施加到环形振荡器。范围控制可操作地控制距离控制参考电流发生器以顺序地改变施加到环形振荡器的范围控制参考电流。耦合到量程控制的锁定检测器比较输出频率信号和参考频率信号，并且响应于比较信号将锁定信号施加到范围控制。响应于所施加的锁定信号，范围控制停止变化范围。锁相环（PLL）电路根据范围控制自动扫描多个频率子范围。控制信号被施加到电压到电流转换器，用于在设定的时间段之后选择性地将电压/电流转换器的操作模式从压缩操作模式控制到未校准的操作模式。该控制信号也适用于量程控制，使范围控制停止变化范围。

5. 发明授权

US06670655B2 SOI CMOS device with body to gate connection 有权
公开(公告)号：US06670655B2
公开(公告)日：2003-12-30
申请号：US09837839
申请日：2001-04-18
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom
IPC分类号： H01L27148
CPC分类号： H01L27/1203 , H01L29/783
摘要： A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

6. 发明授权

US06342793B1 Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain 失效
标题翻译：将大量CMOS控制信号发送到单独的静音模拟电源域的方法和系统
公开(公告)号：US06342793B1
公开(公告)日：2002-01-29
申请号：US09433394
申请日：1999-11-03
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03K190175
CPC分类号： H03K19/00346 , H03K19/017563
摘要： A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T9 and T1 is on and transistors T8 and T0 are off and connection BSEL is pulled high turning on bipolar transistor Q9 allowing current to flow through Q9 and pulling net SB low and selecting inputs B0, B1 to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T8 and T0 is on, and transistors T9 and T1 are off, and connection ASEL is pulled high turning on bipolar transistor Q8 allowing current to flow through Q8 and pulling net SA low and selecting inputs A0, A1 to be transferred to ECL Differential Outputs.
摘要翻译： CMOS信号传输系统，用于将大量的CMOS信号发送到独立的静态模拟电源域。传输系统包括转换器子系统，其提供至少另一个器件级，CMOS信号中的噪声必须通过该器件级流动并被衰减以提供转换的CMOS信号;以及耦合到转换器的多路复用器，其中多路复用器从转换器子接收转换的CMOS信号并且还接收延迟路径控制信号。该转换器包括用于提供高电平电压基准的恒流源和恒定电流两个互补栅极，以及用于通过两个互补栅极从恒定电流源提供到地的路径的两组元件。当CMOS输入信号为高电平且免费CMOS输入信号为低电平时，包括晶体管T9和T1的通过栅导通，晶体管T8和T0断开，并连接BSEL被拉高，双极晶体管Q9导通，允许电流流过Q9并拉动净SB低，并选择输入B0，B1传输到ECL差分输出。同样地，当CMOS输入信号为低电平，并且免费CMOS输入信号为高电平时，包括晶体管T8和T0的通路导通，晶体管T9和T1截止，并且连接ASEL被拉高，导通双极晶体管Q8，允许电流流过 Q8和拉低SA SA，并选择输入A0，A1传输到ECL差分输出。

7. 发明授权

US5831484A Differential charge pump for phase locked loop circuits 失效
标题翻译：差分电荷泵用于锁相环电路
公开(公告)号：US5831484A
公开(公告)日：1998-11-03
申请号：US826436
申请日：1997-03-18
申请人： Eric John Lukes , James David Strom
发明人： Eric John Lukes , James David Strom
IPC分类号： H03L7/089
CPC分类号： H03L7/0895 , H03L7/0896
摘要： A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.
摘要翻译：提供差分电荷泵用于包括差分环路滤波器和共模偏置电路的锁相环（PLL）电路，用于在环路滤波器的高电压滤波器侧上保持预定的偏置电压值。差分电荷泵包括参考电流源。第一和第二电流镜耦合到参考电流源，以提供第一反射镜电流和第二反射镜电流。耦合到第一电流镜的第一开关晶体管接收输入UP信号从环路滤波器的第一侧传导电流。耦合到第二电流镜的第二开关晶体管接收输入的DOWN信号，并且从环路滤波器的第二侧传导电流。第一和第二电流镜和开关晶体管由N沟道金属氧化物半导体（NMOS）器件形成。差分电荷泵能够实现具有低相位误差的大差分输出电压。

8. 发明授权

US06859092B2 Method and low voltage CMOS circuit for generating voltage and current references 失效
标题翻译：用于产生电压和电流参考的方法和低压CMOS电路
公开(公告)号：US06859092B2
公开(公告)日：2005-02-22
申请号：US10418569
申请日：2003-04-17
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
IPC分类号： G05F1/46 , G05F1/10 , G05F3/02
CPC分类号： G05F1/46
摘要： A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.
摘要翻译：提供一种方法和低电压互补金属氧化物半导体（CMOS）电路，用于利用低电压电源产生电压和电流参考。电压产生电路提供电压参考，并由多个CMOS晶体管和电阻器形成。运算放大器包括一对差分CMOS晶体管。第一参考电压被施加到晶体管的差分对的输入和提供第二电压基准的晶体管的差分对的输出。运算放大器包括多个电流参考晶体管。第一电压产生电路产生产生第二电压的第一电压和第二电压产生电路。第一和第二电压产生电路由多个CMOS晶体管形成。产生的第一和第二电压被施加到电压参考产生电路和电流参考晶体管。

9. 发明申请

US20080301503A1 HIGH FREQUENCY DIVIDER STATE CORRECTION CIRCUIT 失效
标题翻译：高频分路器状态校正电路
公开(公告)号：US20080301503A1
公开(公告)日：2008-12-04
申请号：US12187517
申请日：2008-08-07
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： G06F11/28
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

10. 发明授权

US07061284B2 High frequency divider state correction circuit with data path correction 失效
标题翻译：具有数据路径校正的高分频器状态校正电路
公开(公告)号：US07061284B2
公开(公告)日：2006-06-13
申请号：US10850402
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/08
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.
摘要翻译：本发明提供了状态校正。耦合到第二触发器的第一触发器。耦合到第二触发器的输出的状态校正电路。第三触发器耦合到状态校正电路的输出端。第四触发器耦合到第三触发器的输出。

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