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1. 发明授权

US5778243A Multi-threaded cell for a memory 失效
标题翻译：用于内存的多线程单元
公开(公告)号：US5778243A
公开(公告)日：1998-07-07
申请号：US675315
申请日：1996-07-03
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
IPC分类号： G06F12/00 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G11C8/16 , G06F12/02 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/3851 , G11C8/16
摘要： A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.
摘要翻译：一种用于多线程计算机系统中的多线程存储器（和相关方法），其中多个线程与单个处理器一起使用。多线程内存包括：多线程存储单元; 至少一个写入解码器，向所选择的多线程存储单元提供信息; 以及至少一个读取解码器从所选择的多线程存储单元访问信息。每个多线程存储单元包括：N个存储元件，其中N≥2，N个存储元件中的每一个具有线程通信内容; 写入接口，向所述小区内存储元件提供信息; 以及从单元内存储元件读取信息的读取接口。至少一个小区内读取和写入接口至少部分地通过识别对应的线程来选择线程对应内容之一，以实现小区内线程通信的内容选择。

2. 发明授权

US5973971A Device and method for verifying independent reads and writes in a memory array 失效
标题翻译：用于验证存储器阵列中的独立读和写的设备和方法
公开(公告)号：US5973971A
公开(公告)日：1999-10-26
申请号：US2341
申请日：1998-01-02
申请人： Salvatore Nicholas Storino , Gregory John Uhlmann
发明人： Salvatore Nicholas Storino , Gregory John Uhlmann
IPC分类号： G01R31/28 , G11C29/34 , G11C29/36 , G11C29/00
CPC分类号： G11C29/36
摘要： A device and method for verifying independent reads and writes in a memory array includes bit inserters in the array to simultaneously insert a predetermined value into multiple portions of the array. Each row may have a corresponding row bit inserter. Alternatively, or in addition, each memory cell may have a storage element bit inserter. A row bit inserter places a predetermined value at the inputs of a row write port. The storage element bit inserters pre-set memory cells to a predetermined value. To test the read circuitry, storage element bit inserters are set to a predetermined value, and a read is performed. If the value read from a memory cell does not match the value to which it was set, it can be inferred that the read circuitry is not functioning properly. If the values match, it can be inferred that the read circuitry is functioning properly. To test the write circuitry, a row bit inserter may be set to a predetermined value. A write is performed, followed by a read. If the value read from a memory cell matches the value to which the row bit inserter was set, it can be inferred that the write circuitry is functioning properly. If the values do not match, and if it has already been determined that the read circuitry is functioning properly, it can be inferred that the write circuitry is not functioning properly.
摘要翻译：用于验证存储器阵列中的独立读和写的装置和方法包括阵列中的位插入器，以将预定值同时插入阵列的多个部分。每行可以具有相应的行位插入器。或者或另外，每个存储器单元可以具有存储元件位插入器。行位插入器将预定值放置在行写入端口的输入端。存储元件位插入器将存储器单元预先设定为预定值。为了测试读取电路，将存储元件位插入器设置为预定值，并执行读取。如果从存储单元读取的值与其设置的值不匹配，则可以推断读取电路不能正常工作。如果值匹配，则可以推断读取电路正常工作。为了测试写入电路，可以将行位插入器设置为预定值。执行写操作，然后进行读取。如果从存储单元读取的值与设置了行位插入器的值相匹配，则可以推断写入电路正常工作。如果值不匹配，并且如果已经确定读取电路正常工作，则可以推断出写入电路不能正常工作。

3. 发明授权

US07224633B1 eFuse sense circuit 失效
标题翻译： eFuse感应电路
公开(公告)号：US07224633B1
公开(公告)日：2007-05-29
申请号：US11297311
申请日：2005-12-08
申请人： William Paul Hovis , Alan James Leslie , Phil Paone , David W. Siljenberg , Salvatore Nicholas Storino , Gregory John Uhlmann
发明人： William Paul Hovis , Alan James Leslie , Phil Paone , David W. Siljenberg , Salvatore Nicholas Storino , Gregory John Uhlmann
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.
摘要翻译：芯片上的eFuse参考单元提供的参考电压大于由芯片上具有未引脚eFuse的eFuse单元产生的最小电压，但小于由芯片上具有熔丝eFuse的eFuse单元产生的最小电压。参考电流流过eFuse参考电池中的电阻和非吹出eFuse，产生参考电压。参考电压用于在eFuse单元中创建参考电流的镜像副本。参考电流的镜像副本通过eFuse单元中的eFuse流动。比较器接收参考电压和eFuse单元产生的电压。比较器产生一个响应于eFuse电池与参考电压相比产生的电压的输出逻辑电平。

4. 发明授权

US07528646B2 Electrically programmable fuse sense circuit 失效
标题翻译：电可编程保险丝检测电路
公开(公告)号：US07528646B2
公开(公告)日：2009-05-05
申请号：US11550960
申请日：2006-10-19
申请人： Anthony Gus Aipperspach , David Howard Allen , Phil Paone , David Edward Schmitt , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , David Howard Allen , Phil Paone , David Edward Schmitt , Gregory John Uhlmann
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.
摘要翻译：一种具有电可编程熔丝和参考电阻的电可编程熔丝检测电路。第一电流源通过第一开关耦合到电可编程保险丝。第二电流源通过第二开关耦合到参考电阻。预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。当预充电信号不起作用时，第一电流源和第二电流源被切断，同时第一开关和第二开关断开。当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

5. 发明授权

US07489572B2 Method for implementing eFuse sense amplifier testing without blowing the eFuse 有权
标题翻译：实现eFuse读出放大器测试的方法，不用吹efuse
公开(公告)号：US07489572B2
公开(公告)日：2009-02-10
申请号：US11622519
申请日：2007-01-12
申请人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G11C17/165 , G11C17/18 , G11C29/026 , G11C29/027
摘要： A method implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
摘要翻译：一种方法实现对eFuse的读出放大器的有效测试，而不必对eFuse进行编程或打击。在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。这允许检测放大器设备以及下行流连接设备的测试。一旦测试完成，两个预充电装置就一起进行控制。

6. 发明申请

US20080170449A1 Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse 有权
标题翻译：用于实施免费感应放大器测试的方法和设备，不需要吹风
公开(公告)号：US20080170449A1
公开(公告)日：2008-07-17
申请号：US11622519
申请日：2007-01-12
申请人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C17/165 , G11C17/18 , G11C29/026 , G11C29/027
摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
摘要翻译：一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击。在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。这允许检测放大器设备以及下行流连接设备的测试。一旦测试完成，两个预充电装置就一起进行控制。

7. 发明授权

US06629236B1 Master-slave latch circuit for multithreaded processing 有权
标题翻译：用于多线程处理的主从锁存电路
公开(公告)号：US06629236B1
公开(公告)日：2003-09-30
申请号：US09439581
申请日：1999-11-12
申请人： Anthony Gus Aipperspach , Merwin Herscher Alferness , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Merwin Herscher Alferness , Gregory John Uhlmann
IPC分类号： G06F938
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/3851
摘要： A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in a scan mode for testing purposes. In scan mode, one or more elements which normally function as master elements, function as slave elements. When operating in scan mode using this arrangement, the number of master elements in the pair of cells equals the number of slave elements, even though the number of master elements exceeds the number of slave elements during normal operation, permitting data to be successively scanned through all elements of the circuit. In an alternative embodiment, elements function as in scan mode during a HOLD mode of operation, and a feedback loop controlled by a HOLD signal is added to each pair of master/slave elements. The feedback loop drives the master element with the value of the slave.
摘要翻译：用于多线程处理器的主从锁存电路存储多线程的信息。基本单元包含多个主元件，每个主元件对应于相应的线程，耦合到主元件的选择逻辑用于选择主输出中的单个一个，以及耦合到选择器逻辑的单个从元件。优选地，电路支持扫描模式下的操作用于测试目的。在扫描模式中，通常用作主元件的一个或多个元件用作从元件。当使用这种布置在扫描模式下操作时，即使在正常操作期间主元件的数量超过从元件的数量，一对单元中的主元件的数量等于从元件的数量，允许数据被连续地扫描通过电路的所有元素。在替代实施例中，元件在保持操作模式期间起到扫描模式的作用，并且将由HOLD信号控制的反馈回路添加到每对主/从元件。反馈回路以从机的值驱动主元件。

8. 发明授权

US07729188B2 Method and circuit for implementing enhanced eFuse sense circuit 失效
标题翻译：实现增强型eFuse感应电路的方法和电路
公开(公告)号：US07729188B2
公开(公告)日：2010-06-01
申请号：US12029010
申请日：2008-02-11
申请人： Anthony Gus Aipperspach , Phil Christopher Felice Paone , Brian Joy Reed , David Edward Schmitt , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Phil Christopher Felice Paone , Brian Joy Reed , David Edward Schmitt , Gregory John Uhlmann
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , G11C7/062 , G11C7/065 , G11C17/16 , G11C29/026
摘要： A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.
摘要翻译：一种用于实现eFuse读出放大器的方法和电路，以及设置有被摄体电路的设计结构。感测电路包括一对交叉耦合的反相器，每个由一对串联的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）形成。第一上拉电阻耦合在正电压供电轨和感测电路的第一感测节点之间。第二上拉电阻耦合在感测电路的正电压供电轨道和第二感测节点之间。第一位线耦合到感测电路的第一感测节点，耦合到感测电路的第二感测节点的第二位线。相应的参考电阻器和相应的eFuse单元之一选择性地耦合到第一位线和第二位线。

9. 发明授权

US07532057B2 Electrically programmable fuse sense circuit 失效
标题翻译：电可编程保险丝检测电路
公开(公告)号：US07532057B2
公开(公告)日：2009-05-12
申请号：US11872873
申请日：2007-10-16
申请人： Anthony Gus Aipperspach , David Howard Allen , Phil C. Paone , David Edward Schmitt , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , David Howard Allen , Phil C. Paone , David Edward Schmitt , Gregory John Uhlmann
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C17/18 , G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.
摘要翻译：一种用于电可编程熔丝检测电路的设计结构，其具有电可编程熔丝和参考电阻。第一电流源通过第一开关耦合到电可编程保险丝。第二电流源通过第二开关耦合到参考电阻。预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。当预充电信号不起作用时，第一电流源和第二电流源被切断，同时第一开关和第二开关断开。当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

10. 发明授权

US07689950B2 Implementing Efuse sense amplifier testing without blowing the Efuse 失效
标题翻译：实现Efuse感应放大器测试，不会吹动Efuse
公开(公告)号：US07689950B2
公开(公告)日：2010-03-30
申请号：US11872763
申请日：2007-10-16
申请人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , David Howard Allen , Louis Bernard Bushard , Phil Christopher Felice Paone , Gregory John Uhlmann
IPC分类号： G06F17/50
CPC分类号： G11C17/18 , G01R31/07 , G11C17/165 , G11C29/02 , G11C29/026 , G11C29/027
摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
摘要翻译：一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击，并且提供了一个设在该电路中的设计结构。在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。这允许检测放大器设备以及下行流连接设备的测试。一旦测试完成，两个预充电装置就一起进行控制。

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