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    • 1. 发明授权
    • High pressure piezoresistive transducer
    • 高压压阻传感器
    • US5614678A
    • 1997-03-25
    • US596506
    • 1996-02-05
    • Anthony D. KurtzAndrew V. BemisTimothy A. NunnAlexander A. Ned
    • Anthony D. KurtzAndrew V. BemisTimothy A. NunnAlexander A. Ned
    • G01L9/00G01L9/06
    • G01L9/0055
    • A method of fabricating a high pressure piezoresistive pressure transducer having a substantially linear pressure versus stress output over its full range of operation. The method involves bonding a carrier wafer having a dielectric isolating layer on one surface and a supporting member on the opposite surface, to a pattern wafer containing at least two single crystalline longitudinal piezoresistive sensing elements of a second conductivity. Both the pattern wafer and sections of the carrier wafer are etched leaving the piezoresistive sensing elements bonded directly to the dielectric isolating layer, and a diaphragm member having a deflecting portion and a non-deflecting portion. The diaphragm member is constructed to have an aspect ratio which is of the order of magnitude of one. The piezoresistive sensing elements have a large transverse piezoresistive coefficient normal to the plane of the diaphragm and both a large longitudinal piezoresistive coefficient and a small transverse piezoresistive coefficient in the plane of the diaphragm. One of the at least two piezoresistive sensing elements is positioned above the non-deflection portion of the diaphragm in an area of minimal longitudinal stress and the other is positioned above the deflecting portion of the diaphragm in an area of high compressive stress. The positioning of the second sensor over the deflecting portion of the diaphragm is selected so that there will be equal and opposite resistance changes registered from the sensors. The method results in an improved transducer design when compared to prior art devices.
    • 一种制造高压压阻式压力传感器的方法,该压力传感器在其全部操作范围内具有基本线性的压力与应力输出。 该方法包括将具有介电隔离层的载体晶片和相对表面上的支撑构件结合到包含至少两个具有第二导电性的单晶纵向压阻式感测元件的图案晶片。 蚀刻晶片和载体晶片的两个部分,留下直接结合到绝缘隔离层的压阻感测元件,以及具有偏转部分和非偏转部分的隔膜部件。 隔膜构件被构造成具有一个数量级的纵横比。 压阻感测元件具有垂直于隔膜平面的大的横向压阻系数,并且在隔膜平面中具有大的纵向压阻系数和小的横向压阻系数。 至少两个压阻感测元件中的一个在最小纵向应力的区域中位于隔膜的非偏转部分上方,另一个位于隔膜的偏转部分的高压缩应力区域的上方。 选择第二传感器在隔膜的偏转部分上的定位,使得从传感器注册相同和相反的阻力变化。 与现有技术的装置相比,该方法导致改进的换能器设计。
    • 2. 发明授权
    • Method for fabricating a high pressure piezoresistive transducer
    • 制造高压压阻式换能器的方法
    • US5702619A
    • 1997-12-30
    • US723519
    • 1996-09-30
    • Anthony D. KurtzAndrew V. BemisTimothy A. NunnAlexander A. Ned
    • Anthony D. KurtzAndrew V. BemisTimothy A. NunnAlexander A. Ned
    • G01L9/00H01L21/00B44C1/22
    • G01L9/0055
    • A method of fabricating a high pressure piezoresistive pressure transducer having a substantially linear pressure versus stress output over its full range of operation. The method involves bonding a carrier wafer having a dielectric isolating layer on one surface and a supporting member on the opposite surface, to a pattern wafer containing at least two single crystalline longitudinal piezoresistive sensing elements of a second conductivity. Both the pattern wafer and sections of the carrier wafer are etched leaving the piezoresistive sensing elements bonded directly to the dielectric isolating layer, and a diaphragm member having a deflecting portion and a non-deflecting portion. The diaphragm member is constructed to have an aspect ratio which is of the order of magnitude of one. The piezoresistive sensing elements have a large transverse piezoresistive coefficient normal to the plane of the diaphragm and both a large longitudinal piezoresistive coefficient and a small transverse piezoresistive coefficient in the plane of the diaphragm. One of the at least two piezoresistive sensing elements is positioned above the non-deflection portion of the diaphragm in an area of minimal longitudinal stress and the other is positioned above the deflecting portion of the diaphragm in an area of high compressive stress. The positioning of the second sensor over the deflecting portion of the diaphragm is selected so that there will be equal and opposite resistance changes registered from the sensors. The method results in an improved transducer design when compared to prior art devices.
    • 一种制造高压压阻式压力传感器的方法,该压力传感器在其全部操作范围内具有基本线性的压力与应力输出。 该方法包括将具有介电隔离层的载体晶片和相对表面上的支撑构件结合到包含至少两个具有第二导电性的单晶纵向压阻式感测元件的图案晶片。 蚀刻晶片和载体晶片的两个部分,留下直接结合到绝缘隔离层的压阻感测元件,以及具有偏转部分和非偏转部分的隔膜部件。 隔膜构件被构造成具有一个数量级的纵横比。 压阻感测元件具有垂直于隔膜平面的大的横向压阻系数,并且在隔膜平面中具有大的纵向压阻系数和小的横向压阻系数。 至少两个压阻感测元件中的一个在最小纵向应力的区域中位于隔膜的非偏转部分上方,另一个位于隔膜的偏转部分的高压缩应力区域的上方。 选择第二传感器在隔膜的偏转部分上的定位,使得从传感器注册相同和相反的阻力变化。 与现有技术的装置相比,该方法导致改进的换能器设计。
    • 3. 发明授权
    • Pressure transducer employing on-chip resistor compensation
    • 采用片上电阻补偿的压力传感器
    • US06700473B2
    • 2004-03-02
    • US09503678
    • 2000-02-14
    • Anthony D. KurtzAndrew V. BemisJoseph VanDeWeert
    • Anthony D. KurtzAndrew V. BemisJoseph VanDeWeert
    • H01L1010
    • G01L1/2281G01L9/0055G01L9/065
    • A dielectrically isolated temperature compensated pressure transducer including: a wafer including a deflectable diaphragm formed therein, the diaphragm being capable of deflecting in response to an applied pressure, and the diaphragm defining an active region surrounded by an inactive region of the wafer; a plurality of dielectrically isolated piezoresistive elements formed on the active region of the wafer and coupled together to form a Wheatstone bridge configuration so as to cooperatively provide an output signal in response to and indicative of an amount of deflection of the diaphragm, the plurality of piezoresistive elements being undesirably operative to introduce an undesirable error into the output according to exposure of the wafer to an environmental condition; and, a dielectrically isolated resistor formed on the inactive region of the wafer and electrically coupled in series to the plurality of piezoresistive elements so as to at least partially compensate for the undesirable error.
    • 一种介电隔离的温度补偿压力传感器,包括:晶片,其包括形成在其中的可偏转光阑,所述光阑能够响应于所施加的压力而偏转,并且所述光阑限定由所述晶片的非活动区域包围的有源区域; 形成在晶片的有源区上并耦合在一起以形成惠斯登电桥结构的多个介电离子压阻元件,以协同地提供输出信号以响应并指示隔膜的偏转量,多个压阻 元件不合需要地操作以根据晶片暴露于环境条件而将不期望的误差引入到输出中; 以及形成在所述晶片的非活性区域上的电介质隔离的电阻器,其电耦合到所述多个压阻元件,以便至少部分地补偿所述不期望的误差。
    • 4. 发明授权
    • Dielectrically isolated well structures
    • 介电隔离井结构
    • US5789793A
    • 1998-08-04
    • US822077
    • 1997-03-20
    • Anthony D. KurtzAndrew V. Bemis
    • Anthony D. KurtzAndrew V. Bemis
    • H01L21/762H07L21/76
    • H01L21/76264H01L21/76275H01L21/76283
    • A method for fabricating a semiconductor device comprising fabricating a sacrificial wafer having a substrate wafer which includes a diffused layer and one or two epi layers. The sacrificial wafer is fusion bonded to a separately fabricated carrier/handle wafer having a layer of oxide on its surface, to form a composite wafer. Selective regions of the composite wafer are anodized and oxidized to form a plurality of wells separated from each other by a dielectric insulating layer. Next, N- epi regions above P+ epi regions are removed or alternatively, P+ diffused layers are removed from above an N- epi layer in selected regions. Finally, P- or N- single crystal silicon is grown back to the removed regions, depending on how the regions were removed. If N- single crystal is grown back to the removed regions, a high temperature drive-in is employed to finish the processing. The final structure contains N and P regions which are dielectrically isolated from each other and from the substrate. The isolated well structure can now be used to house circuit elements such as resistors, diodes, transistors, scrs, etc., individually or multiply as desired.
    • 一种用于制造半导体器件的方法,包括制造具有包括扩散层和一个或两个外延层的衬底晶片的牺牲晶片。 牺牲晶片被熔接到单独制造的载体/处理晶片上,其具有在其表面上的一层氧化物,以形成复合晶片。 复合晶片的选择区被阳极氧化并氧化形成通过介电绝缘层彼此分离的多个阱。 接下来,除去P +外延区以上的N-epi区,或者替代地,在选定区中从N外延层上方去除P +扩散层。 最后,取决于如何去除区域,P-或N-单晶硅生长回去除的区域。 如果N-单晶生长回去除的区域,则采用高温驱入来完成处理。 最终结构包含彼此介质和从基底介电隔离的N和P区。 隔离的井结构现在可以用于容纳电路元件,例如电阻器,二极管,晶体管,scrs等,根据需要单独或乘法。
    • 5. 发明授权
    • Dielectrically isolated SiC mosfet
    • 电介质隔离SiC mosfet
    • US5574295A
    • 1996-11-12
    • US512892
    • 1995-08-09
    • Anthony D. KurtzAndrew V. Bemis
    • Anthony D. KurtzAndrew V. Bemis
    • H01L21/04H01L29/24H01L29/423H01L29/786H01L31/0312H01L29/00H01L29/80
    • H01L29/1608H01L29/42384H01L29/66068H01L29/78684
    • A metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a carrier wafer and a silicon gate region disposed on the carrier wafer. A source region and a drain region made from 3C-silicon carbide are disposed on the carrier wafer above the gate region. A gate oxide, derived from silicon, separates the source and drain regions from the gate region. Laterally oriented oxide trenches separate and dielectrically isolate the MOSFET device from other devices on the carrier wafer. Further, the MOSFET device described above is manufactured in a method comprising the steps of providing a carrier wafer having an oxide layer formed on a surface thereof. A layer of silicon having a given level of conductivity is bonded to the oxide layer of the carrier wafer. Selected portions of the layer of silicon are oxidized to create a plurality of dielectrically isolated silicon islands, one of which forms a gate region. A layer of silicon dioxide is then formed over the dielectrically isolated islands of silicon. Two layers of silicon carbide are then bonded to the layer of silicon dioxide. A source region and a drain region are each formed from the layers of silicon carbide. Selected portions of one of the two layers of silicon carbide are oxidized to dielectrically isolate the source region and the drain region from other semiconductor devices located on the carrier wafer.
    • 包括载体晶片和设置在载体晶片上的硅栅极区域的金属氧化物半导体场效应晶体管(MOSFET)器件。 由3C-碳化硅制成的源极区域和漏极区域设置在栅极区域上方的载体晶片上。 从硅衍生的栅极氧化物从栅极区域分离源极和漏极区域。 侧向取向的氧化物沟槽分离并介电地将MOSFET器件与载体晶片上的其它器件隔离。 此外,上述MOSFET器件以包括以下步骤的方法制造:提供在其表面上形成有氧化物层的载体晶片。 具有给定电导率的硅层被结合到载体晶片的氧化物层上。 硅层的选定部分被氧化以产生多个介电隔离的硅岛,其中之一形成栅极区。 然后在介电离子的硅岛上形成一层二氧化硅。 然后将两层碳化硅结合到二氧化硅层。 源极区域和漏极区域各自由碳化硅层形成。 两个碳化硅层之一的选定部分被氧化,以将源极区和漏极区域与位于载体晶片上的其它半导体器件介电隔离。