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1. 发明授权

US08392866B2 Task-based multi-process design synthesis with notification of transform signatures 有权
标题翻译：基于任务的多进程设计综合与转换签名通知
公开(公告)号：US08392866B2
公开(公告)日：2013-03-05
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

2. 发明申请

US20120159418A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES 有权
标题翻译：基于任务的多进程设计合成与变换签名的通知
公开(公告)号：US20120159418A1
公开(公告)日：2012-06-21
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

3. 发明授权

US08407652B2 Task-based multi-process design synthesis 有权
标题翻译：基于任务的多进程设计综合
公开(公告)号：US08407652B2
公开(公告)日：2013-03-26
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

4. 发明授权

US08341565B2 Task-based multi-process design synthesis with reproducible transforms 有权
标题翻译：基于任务的多进程设计合成与可重现的转换
公开(公告)号：US08341565B2
公开(公告)日：2012-12-25
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

5. 发明申请

US20120159417A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS 有权
标题翻译：基于任务的多进程设计合成
公开(公告)号：US20120159417A1
公开(公告)日：2012-06-21
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

6. 发明申请

US20120159406A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS 有权
标题翻译：基于任务的多进程设计与可重构变换的合成
公开(公告)号：US20120159406A1
公开(公告)日：2012-06-21
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

7. 发明申请

US20100042955A1 Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design 有权
标题翻译：最大限度地减少对芯片设计造成最小影响的早期模式违规方法
公开(公告)号：US20100042955A1
公开(公告)日：2010-02-18
申请号：US12191435
申请日：2008-08-14
申请人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

8. 发明授权

US07996812B2 Method of minimizing early-mode violations causing minimum impact to a chip design 有权
标题翻译：最小化早期模式违规的方法，对芯片设计造成的影响最小
公开(公告)号：US07996812B2
公开(公告)日：2011-08-09
申请号：US12191435
申请日：2008-08-14
申请人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

9. 发明申请

US20120054699A1 CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE MICROPROCESSOR DESIGNS 有权
标题翻译：用于高性能微处理器设计的大块和结构化合成
公开(公告)号：US20120054699A1
公开(公告)日：2012-03-01
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

10. 发明授权

US08271920B2 Converged large block and structured synthesis for high performance microprocessor designs 有权
标题翻译：用于高性能微处理器设计的融合大块和结构化合成
公开(公告)号：US08271920B2
公开(公告)日：2012-09-18
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

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