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1. 发明授权

US08365114B2 Logic modification synthesis 有权
标题翻译：逻辑修改综合
公开(公告)号：US08365114B2
公开(公告)日：2013-01-29
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.
摘要翻译：正在识别两个电路，一个原始和一个修改的电路，原始电路具有第一逻辑，并且该修改的电路具有第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化。在原始电路中检测到等效线，使得第一和第二逻辑等效于从电路输入到等价线。至少一个变化点位于与等价线相邻的逻辑门之间。如果可观察性条件得到满足，则可以接受更改点。可观察性条件在布尔满足度（SAT）公式中进行检查。通过使用SAT和布尔方程求解技术，使得第一逻辑变为等同于第二逻辑的方式，导出用于验证的变化点的替代逻辑。

2. 发明申请

US20120054699A1 CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE MICROPROCESSOR DESIGNS 有权
标题翻译：用于高性能微处理器设计的大块和结构化合成
公开(公告)号：US20120054699A1
公开(公告)日：2012-03-01
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

3. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

4. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

5. 发明授权

US08271920B2 Converged large block and structured synthesis for high performance microprocessor designs 有权
标题翻译：用于高性能微处理器设计的融合大块和结构化合成
公开(公告)号：US08271920B2
公开(公告)日：2012-09-18
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

6. 发明申请

US20120054698A1 LOGIC MODIFICATION SYNTHESIS 有权
标题翻译：逻辑修改合成
公开(公告)号：US20120054698A1
公开(公告)日：2012-03-01
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer-executed method is disclosed which recognizes two circuits, an original and a modified circuit, with the original circuit having a first logic and the modified circuit having a second logic. The second logic is obtained by converting a modified specification into a preliminary gate-level form. The second logic contains at least one desired logic change relative to the first logic in order to realize the modified specification. The method includes detecting an equivalence line in the original circuit, such that the first and second logic are equivalent from the circuit inputs to the equivalence line, and finding at least one point of change amongst the logic gates that are neighboring the equivalence line. Next, accepting the points of change as verified point of change if an observability condition is fulfilled, which means that for every input vector for which an output of the original and modified circuits differ, at least one logic value of the points of change propagate to that output of the original circuit. This observability condition is checked within a Boolean Satisfiability (SAT) formulation. The method also includes deriving a substitute logic for the verified points of change, using SAT techniques, and Boolean equation solving techniques which solve for a change function at each point of change, in such manner that the first logic in the original circuit becomes equivalent to the second logic, and thereby implements the changed specification.
摘要翻译：公开了一种计算机执行方法，其识别具有第一逻辑的原始电路的两个电路，原始电路和修改的电路，并且修改的电路具有第二逻辑。通过将修改的规范转换成初级门级形式来获得第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化，以便实现修改的规范。该方法包括检测原始电路中的等效线，使得第一和第二逻辑等效于从等效线路的电路输入，并找到与等价线相邻的逻辑门之间的至少一个变化点。接下来，如果满足可观察性条件，则将变化点接受为经验证的变化点，这意味着对于原始和修正电路的输出不同的每个输入向量，改变点的至少一个逻辑值传播到原始电路的输出。在布尔满足度（SAT）公式中检查此可观察性条件。该方法还包括使用SAT技术，以及在每个变化点解决变化函数的布尔方程求解技术，以使得原始电路中的第一逻辑等同于第二个逻辑，从而实现改变的规范。

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