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1. 发明申请

US20100165747A1 NON-VOLATILE MEMORY CELL HEALING 有权
标题翻译：非易失性记忆细胞治疗
公开(公告)号：US20100165747A1
公开(公告)日：2010-07-01
申请号：US12721165
申请日：2010-03-10
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

2. 发明授权

US08542542B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US08542542B2
公开(公告)日：2013-09-24
申请号：US13567729
申请日：2012-08-06
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

3. 发明授权

US08238170B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US08238170B2
公开(公告)日：2012-08-07
申请号：US12721165
申请日：2010-03-10
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

4. 发明授权

US07701780B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US07701780B2
公开(公告)日：2010-04-20
申请号：US11809180
申请日：2007-05-31
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

5. 发明申请

US20080298123A1 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US20080298123A1
公开(公告)日：2008-12-04
申请号：US11809180
申请日：2007-05-31
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

6. 发明申请

US20120300551A1 NON-VOLATILE MEMORY CELL HEALING 有权
标题翻译：非易失性记忆细胞治疗
公开(公告)号：US20120300551A1
公开(公告)日：2012-11-29
申请号：US13567729
申请日：2012-08-06
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，并且向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

7. 发明申请

US20080151646A1 FLASH MEMORY DEVICE WITH IMPROVED ERASE OPERATION 有权
标题翻译：具有改进的擦除操作的闪存存储器件
公开(公告)号：US20080151646A1
公开(公告)日：2008-06-26
申请号：US11614820
申请日：2006-12-21
申请人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
发明人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16
摘要： Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括具有耦合到半导体衬底的阱的存储器单元的器件和耦合在存储器单元和器件的位线之间的选择晶体管。器件可以具有第一电路，以在擦除操作期间将阱的阱电压从第一阱电压电平升高到第二阱电压电平。在擦除操作期间，第一电路可以将阱保持在第二阱电压电平一段时间间隔。器件可以具有第二电路，以将选择晶体管的栅极的电压从第一栅极电压电平升高到可能低于第二阱电压电平的第二栅极电压电平。第二电路可以在擦除操作期间将栅极保持在第二栅极电压电平一段时间间隔。公开了包括附加装置，系统和方法的其它实施例。

8. 发明授权

US07499325B2 Flash memory device with improved erase operation 有权
标题翻译：闪存器件具有改进的擦除操作
公开(公告)号：US07499325B2
公开(公告)日：2009-03-03
申请号：US11614820
申请日：2006-12-21
申请人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
发明人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16
摘要： Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括具有耦合到半导体衬底的阱的存储器单元的器件和耦合在存储器单元和器件的位线之间的选择晶体管。器件可以具有第一电路，以在擦除操作期间将阱的阱电压从第一阱电压电平升高到第二阱电压电平。在擦除操作期间，第一电路可以将阱保持在第二阱电压电平一段时间间隔。器件可以具有第二电路，以将选择晶体管的栅极的电压从第一栅极电压电平升高到可能低于第二阱电压电平的第二栅极电压电平。第二电路可以在擦除操作期间将栅极保持在第二栅极电压电平一段时间间隔。公开了包括附加装置，系统和方法的其它实施例。

9. 发明授权

US09202536B2 Three dimensional memory control circuitry 有权
标题翻译：三维存储器控制电路
公开(公告)号：US09202536B2
公开(公告)日：2015-12-01
申请号：US13995044
申请日：2012-03-26
申请人： Mark Helm , Jung Sheng Hoei , Aaron Yip , Dzung Nguyen
发明人： Mark Helm , Jung Sheng Hoei , Aaron Yip , Dzung Nguyen
IPC分类号： G11C16/04 , G11C7/12 , G11C7/18 , G11C8/14 , H01L27/02 , H01L27/06 , H01L27/105 , H01L27/115 , G11C5/02 , G11C5/12 , G11C13/00 , G11C16/24
CPC分类号： G11C16/26 , G11C5/025 , G11C5/12 , G11C7/12 , G11C7/18 , G11C8/14 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C16/24 , H01L27/0207 , H01L27/0688 , H01L27/1052 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11573 , H01L27/11582 , Y10T29/49155
摘要： An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
摘要翻译：集成电路包括存储器阵列，字线电路，被划分为至少两个子电路以控制存储器阵列;以及位线电路，被划分为至少两个子电路以控制存储器阵列。字线子电路和位线子电路至少部分地与存储器阵列的相应区域重叠。

10. 发明授权

US08053321B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US08053321B2
公开(公告)日：2011-11-08
申请号：US12834231
申请日：2010-07-12
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

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