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1. 发明授权

US08053321B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US08053321B2
公开(公告)日：2011-11-08
申请号：US12834231
申请日：2010-07-12
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

2. 发明授权

US07413946B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US07413946B2
公开(公告)日：2008-08-19
申请号：US11566355
申请日：2006-12-04
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8236 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

3. 发明授权

US07304353B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US07304353B2
公开(公告)日：2007-12-04
申请号：US11146812
申请日：2005-06-07
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

4. 发明申请

US20070093016A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20070093016A1
公开(公告)日：2007-04-26
申请号：US11566350
申请日：2006-12-04
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整中的至少一个以及多晶硅栅极堆叠掺杂来控制每个器件Vt的性能特征和控制。

5. 发明申请

US20090286366A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20090286366A1
公开(公告)日：2009-11-19
申请号：US12512631
申请日：2009-07-30
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

6. 发明授权

US07755146B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US07755146B2
公开(公告)日：2010-07-13
申请号：US12512631
申请日：2009-07-30
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

7. 发明授权

US07696579B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 失效
公开(公告)号：US07696579B2
公开(公告)日：2010-04-13
申请号：US11877744
申请日：2007-10-24
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

8. 发明授权

US07439140B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US07439140B2
公开(公告)日：2008-10-21
申请号：US11566350
申请日：2006-12-04
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整中的至少一个以及多晶硅栅极堆叠掺杂来控制每个器件Vt的性能特征和控制。

9. 发明授权

US07189607B2 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
公开(公告)号：US07189607B2
公开(公告)日：2007-03-13
申请号：US10931891
申请日：2004-09-01
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

10. 发明申请

US20060003513A1 Formation of standard voltage threshold and low voltage threshold MOSFET devices 有权
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20060003513A1
公开(公告)日：2006-01-05
申请号：US11216632
申请日：2005-08-31
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt器件的衬底中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

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