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1. 发明申请

US20080151646A1 FLASH MEMORY DEVICE WITH IMPROVED ERASE OPERATION 有权
标题翻译：具有改进的擦除操作的闪存存储器件
公开(公告)号：US20080151646A1
公开(公告)日：2008-06-26
申请号：US11614820
申请日：2006-12-21
申请人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
发明人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16
摘要： Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括具有耦合到半导体衬底的阱的存储器单元的器件和耦合在存储器单元和器件的位线之间的选择晶体管。器件可以具有第一电路，以在擦除操作期间将阱的阱电压从第一阱电压电平升高到第二阱电压电平。在擦除操作期间，第一电路可以将阱保持在第二阱电压电平一段时间间隔。器件可以具有第二电路，以将选择晶体管的栅极的电压从第一栅极电压电平升高到可能低于第二阱电压电平的第二栅极电压电平。第二电路可以在擦除操作期间将栅极保持在第二栅极电压电平一段时间间隔。公开了包括附加装置，系统和方法的其它实施例。

2. 发明授权

US07499325B2 Flash memory device with improved erase operation 有权
标题翻译：闪存器件具有改进的擦除操作
公开(公告)号：US07499325B2
公开(公告)日：2009-03-03
申请号：US11614820
申请日：2006-12-21
申请人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
发明人： Daniel H. Doyle , Mark Helm , Andrei Mihnea
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16
摘要： Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括具有耦合到半导体衬底的阱的存储器单元的器件和耦合在存储器单元和器件的位线之间的选择晶体管。器件可以具有第一电路，以在擦除操作期间将阱的阱电压从第一阱电压电平升高到第二阱电压电平。在擦除操作期间，第一电路可以将阱保持在第二阱电压电平一段时间间隔。器件可以具有第二电路，以将选择晶体管的栅极的电压从第一栅极电压电平升高到可能低于第二阱电压电平的第二栅极电压电平。第二电路可以在擦除操作期间将栅极保持在第二栅极电压电平一段时间间隔。公开了包括附加装置，系统和方法的其它实施例。

3. 发明申请

US20100165747A1 NON-VOLATILE MEMORY CELL HEALING 有权
标题翻译：非易失性记忆细胞治疗
公开(公告)号：US20100165747A1
公开(公告)日：2010-07-01
申请号：US12721165
申请日：2010-03-10
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

4. 发明申请

US20120300551A1 NON-VOLATILE MEMORY CELL HEALING 有权
标题翻译：非易失性记忆细胞治疗
公开(公告)号：US20120300551A1
公开(公告)日：2012-11-29
申请号：US13567729
申请日：2012-08-06
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，并且向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

5. 发明授权

US08542542B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US08542542B2
公开(公告)日：2013-09-24
申请号：US13567729
申请日：2012-08-06
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

6. 发明授权

US08238170B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US08238170B2
公开(公告)日：2012-08-07
申请号：US12721165
申请日：2010-03-10
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

7. 发明授权

US07701780B2 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US07701780B2
公开(公告)日：2010-04-20
申请号：US11809180
申请日：2007-05-31
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

8. 发明申请

US20080298123A1 Non-volatile memory cell healing 有权
标题翻译：非易失性记忆细胞愈合
公开(公告)号：US20080298123A1
公开(公告)日：2008-12-04
申请号：US11809180
申请日：2007-05-31
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

9. 发明授权

US08575715B2 Punch-through diode steering element 有权
标题翻译：穿通二极管转向元件
公开(公告)号：US08575715B2
公开(公告)日：2013-11-05
申请号：US13571100
申请日：2012-08-09
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L29/66
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

10. 发明授权

US08514629B2 Method for memory cell erasure with a programming monitor of reference cells 有权
标题翻译：用参考单元的编程监视器进行存储单元擦除的方法
公开(公告)号：US08514629B2
公开(公告)日：2013-08-20
申请号：US13602762
申请日：2012-09-04
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

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