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1. 发明授权

US07379924B1 Quantifying and predicting the impact of line edge roughness on device reliability and performance 失效
标题翻译：量化和预测线边缘粗糙度对器件可靠性和性能的影响
公开(公告)号：US07379924B1
公开(公告)日：2008-05-27
申请号：US11001151
申请日：2004-12-01
申请人： Amit P. Marathe , Calvin T. Gabriel
发明人： Amit P. Marathe , Calvin T. Gabriel
IPC分类号： G06F15/18 , G05B13/00
CPC分类号： H01L22/20
摘要： Systems and methods are disclosed for testing semiconductors at the wafer level, specifically, systems and methods are disclosed that quantify line-edge roughness in terms of electrical properties and the impact of the line-edge roughness on device reliability and performance. A voltage ramp dielectric breakdown (VRDB) test is used to measure the breakdown voltage of the inter-digitated fingers of a semiconductor device. The distribution of breakdown voltage is used to measure the median breakdown voltage and the outliers which fan the extrinsic tail. Thereby, VRDB is used to quantify the impact LER will have on device reliability and performance. The systems and methods also provide a feedback tool to the fabrication process to control line edge roughness to a desired specification.
摘要翻译：公开了用于在晶片级测试半导体的系统和方法，具体地，公开了在电特性方面量化线边缘粗糙度以及线边缘粗糙度对器件可靠性和性能的影响的系统和方法。使用电压斜坡绝缘击穿（VRDB）测试来测量半导体器件的数字间指状物的击穿电压。击穿电压的分布用于测量中间击穿电压和外来尾部的异常值。因此，VRDB用于量化LER对器件可靠性和性能的影响。这些系统和方法还为制造过程提供反馈工具，以将线边缘粗糙度控制到期望的规格。

2. 发明授权

US06391766B1 Method of making a slot via filled dual damascene structure with middle stop layer 有权
标题翻译：通过具有中间停止层的填充双镶嵌结构制作槽的方法
公开(公告)号：US06391766B1
公开(公告)日：2002-05-21
申请号：US09788641
申请日：2001-02-21
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An inorganic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种形成互连结构的方法，其中有机低k介电材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。狭缝通孔比随后形成的沟槽的宽度长。无机低k介电材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

3. 发明授权

US6057245A Gas phase planarization process for semiconductor wafers 失效
公开(公告)号：US6057245A
公开(公告)日：2000-05-02
申请号：US233640
申请日：1999-01-19
申请人： Rao V. Annapragada , Calvin T. Gabriel , Milind G. Weling
发明人： Rao V. Annapragada , Calvin T. Gabriel , Milind G. Weling
IPC分类号： H01L21/3205 , B24B7/22 , B24D13/14 , H01L21/304 , H01L21/3105 , H01L21/302
CPC分类号： B24B7/228 , B24D13/14 , H01L21/31053
摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

4. 发明授权

US5990561A Tungsten plugs for integrated circuits and methods for making same 失效
标题翻译：用于集成电路的钨插头及其制造方法
公开(公告)号：US5990561A
公开(公告)日：1999-11-23
申请号：US97318
申请日：1998-06-12
申请人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
发明人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53257 , H01L2924/0002
摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.
摘要翻译：根据本发明的使用钨丝塞的集成电路胶层的制造方法包括：（A）提供具有表面，中心，边缘和与该表面垂直的方向的基板; 和（B）在衬底的表面上溅射沉积胶层，使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105％层在垂直于衬底中心表面的方向上测量。在一些实施例中，在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105％至150％的范围内，其测量方向是垂直于在基板的中心处的表面，例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110％至120％的范围内。

5. 发明授权

US5804502A Tungsten plugs for integrated circuits and methods for making same 失效
公开(公告)号：US5804502A
公开(公告)日：1998-09-08
申请号：US786366
申请日：1997-01-16
申请人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
发明人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53257 , H01L2924/0002
摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

6. 发明授权

US5702978A Sloped silicon nitride etch for smoother field oxide edge 失效
标题翻译：用于平滑的场氧化物边缘的斜面氮化硅蚀刻
公开(公告)号：US5702978A
公开(公告)日：1997-12-30
申请号：US640092
申请日：1996-04-30
申请人： Calvin T. Gabriel , Olivier F. Laparra
发明人： Calvin T. Gabriel , Olivier F. Laparra
IPC分类号： H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： A method of fabricating an integrated circuit on a silicon substrate in such a manner as to avoid the requirement of over-etching the polysilicon usually necessary to prevent shorting of adjacent devices by poly filaments caused by deep polysilicon pockets in notch areas created in the field oxide during its growth. The notches are prevented by forming the nitride mask with sloped rather than perpendicular side walls. The sloped side walls present less resistance to the growing oxide than does the usual perpendicular wall and thus does not dig into the growing oxide to form the notches. The edge of the resultant field oxide is therefore smoother, permitting easier and more complete removal of the polysilicon without the need for over-etching.
摘要翻译：一种在硅衬底上制造集成电路的方法，以避免过度蚀刻通常必需的多晶硅的需要，以防止由在场氧化物中产生的缺口区域中的深多晶硅袋引起的由多晶丝短路的多晶丝在它的成长期间。通过用倾斜而不是垂直的侧壁形成氮化物掩模来防止缺口。倾斜的侧壁比通常的垂直壁对生长的氧化物具有较小的抵抗力，因此不会进入生长的氧化物以形成凹口。因此，所得到的场氧化物的边缘更平滑，允许更容易且更完全地去除多晶硅，而不需要过度蚀刻。

7. 发明授权

US5639697A Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing 失效
标题翻译：用于改善化学机械抛光过程中去除率一致性的虚拟底层
公开(公告)号：US5639697A
公开(公告)日：1997-06-17
申请号：US593900
申请日：1996-01-30
申请人： Milind G. Weling , Subhas Bothra , Calvin T. Gabriel
发明人： Milind G. Weling , Subhas Bothra , Calvin T. Gabriel
IPC分类号： H01L21/3105 , H01L21/302 , H01L21/463
CPC分类号： H01L21/31053 , Y10S438/926
摘要： A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.
摘要翻译：公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。在一些实施例中，预定图案密度在大约40％至80％的范围内。在一些应用中，活性导电迹线和虚拟凸起线都由金属材料形成，该金属材料在化学机械抛光过程之前在一个步骤中沉积，绝缘层沉积在两个有源导电迹线和虚拟凸起线上。在其他应用中，假凸起线由绝缘层形成。

8. 发明授权

US5462892A Semiconductor processing method for preventing corrosion of metal film connections 失效
标题翻译：用于防止金属膜连接腐蚀的半导体加工方法
公开(公告)号：US5462892A
公开(公告)日：1995-10-31
申请号：US180193
申请日：1994-01-11
申请人： Calvin T. Gabriel
发明人： Calvin T. Gabriel
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/283 , H01L21/31
CPC分类号： H01L21/02071 , H01L21/76886 , Y10S148/015
摘要： A semiconductor wafer is processed so as to inhibit corrosion of aluminum or other metal interconnection lines thereon. The anti-corrosion processing of the wafer takes place after forming a metal layer on a semiconductor wafer, masking the metal layer with resist and reactive ion etching the conductive layer in an evacuated chamber so as to form metal interconnection lines. The semiconductor wafer is then moved under vacuum to a second evacuated chamber, where an oxide is formed on sidewalls of the metal layer by heating the semiconductor wafer while flowing dry oxygen-containing gas. The oxide on the sidewalls of the metal layer prevents corrosion of the metal layer by reactive halogen compounds remaining on the semiconductor wafer after the reactive ion etching step. The resist remaining on the wafer is removed after the semiconductor wafer is removed from the second evacuated chamber. Typically, the metal layer is formed from aluminum or aluminum-copper alloy, or from a successive layers of tungsten/titanium and aluminum-copper. The oxide formation step is preferably performed by heating the wafer to a temperature not exceeding 450.degree. C. while flowing dry oxygen-containing gas, at a pressure or about one atmosphere or less, through the second evacuated chamber.
摘要翻译：处理半导体晶片以便抑制其上的铝或其它金属互连线的腐蚀。在半导体晶片上形成金属层之后，利用抗蚀剂掩蔽金属层并在真空室中对导电层进行反应离子蚀刻，形成金属互连线，进行晶片的防腐处理。然后将半导体晶片在真空下移动到第二真空室，其中通过在流过干含氧气体的同时加热半导体晶片而在金属层的侧壁上形成氧化物。在金属层的侧壁上的氧化物防止在反应离子蚀刻步骤之后残留在半导体晶片上的活性卤素化合物对金属层的腐蚀。在将半导体晶片从第二抽空室移除之后，去除残留在晶片上的抗蚀剂。通常，金属层由铝或铝 - 铜合金形成，或者由钨/钛和铝 - 铜的连续层形成。氧化物形成步骤优选通过将晶片加热至不超过450℃的温度，同时通过第二抽真空室在约一个或几个大气压或更低的压力下使干燥含氧气体流动。

9. 发明授权

US5294295A Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges 失效
标题翻译：使用氮化硅隔离保护氧化物钝化边缘的集成电路的湿气密封方法
公开(公告)号：US5294295A
公开(公告)日：1994-03-15
申请号：US786322
申请日：1991-10-31
申请人： Calvin T. Gabriel
发明人： Calvin T. Gabriel
IPC分类号： H01L21/314 , H01L23/31 , B44C1/22
CPC分类号： H01L23/3192 , H01L23/3171 , H01L2924/0002 , Y10S148/043 , Y10S438/958
摘要： For passivation of an integrated circuit device, a film of silicon dioxide is deposited over the integrated circuit device. A film of silicon nitride is deposited over the film of silicon dioxide. The film of silicon nitride and the film of silicon dioxide are etched using a single passivation mask to expose the bond pads of the integrated circuit device. Spacer regions of silicon nitride are placed over edges of the film of silicon dioxide exposed by the etching. The spacer regions may be placed by depositing a second film of silicon nitride over the film of silicon nitride. This second film of silicon nitride covers the metal bond pads and the exposed edges of the film of silicon dioxide. An anisotropic etchback of the second film of silicon nitride is performed to expose the metal bond pads while leaving spacer regions which cover the edges of the film of silicon dioxide.
摘要翻译：对于集成电路器件的钝化，二氧化硅膜沉积在集成电路器件上。氮化硅膜沉积在二氧化硅膜上。使用单个钝化掩模蚀刻氮化硅膜和二氧化硅膜以暴露集成电路器件的接合焊盘。氮化硅的间隔区被放置在通过蚀刻暴露的二氧化硅膜的边缘上。可以通过在氮化硅膜上沉积第二氮化硅膜来放置间隔区。该第二氮化硅膜覆盖金属接合焊盘和二氧化硅膜的暴露边缘。执行第二氮化硅膜的各向异性回蚀以暴露金属接合焊盘，同时留下覆盖二氧化硅膜的边缘的间隔区。

10. 发明授权

US06864184B1 Method for reducing critical dimension attainable via the use of an organic conforming layer 失效
标题翻译：通过使用有机符合层可以降低临界尺寸的方法
公开(公告)号：US06864184B1
公开(公告)日：2005-03-08
申请号：US10772830
申请日：2004-02-05
申请人： Calvin T. Gabriel
发明人： Calvin T. Gabriel
IPC分类号： H01L21/033 , H01L21/308 , H01L21/311 , H01L21/768 , H01L21/302
CPC分类号： H01L21/3081 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/31144 , H01L21/76816
摘要： In one embodiment, a semiconductor device processing method, comprising the steps of: (a) using a patterned photoresist to form a structure having at least one edge; (b) prior to removal of the photoresist, forming a conforming layer from an organic compound and patterning the conforming layer to form at least one sidewall spacer which are self-aligned to the at least one edge; (c) performing a processing operation which is at least partially localized by the at least one sidewall spacer; and (d) removing the at least one sidewall spacer and the photoresist, wherein the conforming layer is formed via deposition of at least one organic compound selected from C1 to C8 alkanes C2 to C8 alkenes, C3 to C8 cyclo-alkenes, C4 to C8 cyclo-alkenes, C1 to C8 fluoro-alkanes, C2 to C8 fluoro-alkenes, C3 to C8 cyclofluoro-alkanes, C4 to C8 cyclofluoro-alkenes, or mixtures thereof.
摘要翻译：在一个实施例中，一种半导体器件处理方法，包括以下步骤：（a）使用图案化的光致抗蚀剂以形成具有至少一个边缘的结构; （b）在去除光致抗蚀剂之前，从有机化合物形成合适的层，并构图所述适形层以形成至少一个与所述至少一个边缘自对准的侧壁间隔物; （c）执行由所述至少一个侧壁间隔件至少部分定位的处理操作; 和（d）去除所述至少一个侧壁间隔物和所述光致抗蚀剂，其中通过沉积至少一种选自C1至C8烷烃C2至C8烯烃，C3至C8环烯烃，C4至C8的有机化合物形成所述一致层环烯烃，C1至C8氟代烷烃，C2至C8氟代烯烃，C3至C8环氟烷烃，C4至C8环氟烯烃或其混合物。

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