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1. 发明授权

US06939803B2 Method for forming conductor reservoir volume for integrated circuit interconnects 有权
标题翻译：用于形成集成电路互连的导体储存器容积的方法
公开(公告)号：US06939803B2
公开(公告)日：2005-09-06
申请号：US10225656
申请日：2002-08-21
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。器件介电层上的第一介电层具有形成在其中的开口，其中包括导体储存器体积。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。除了第一通道开口之外，阻挡层沿着第二通道和通孔开口。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。导体储存器容积提供导体材料供应，以防止在第一通道和通孔中形成空隙。

2. 发明授权

US06710452B1 Coherent diffusion barriers for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干扩散屏障
公开(公告)号：US06710452B1
公开(公告)日：2004-03-23
申请号：US09618964
申请日：2000-07-19
申请人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L21/76886 , H01L21/76888 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。阻挡层具有比通道介电层更加负的形成热量，由此阻挡层与导体芯的材料扩散到沟道介电层上形成阻挡层。阻挡层还与导体芯形成稳定的化合物，以形成将沟道电介质结合到导体芯的相干势垒层。

3. 发明授权

US06621290B1 Characterization of barrier layers in integrated circuit interconnects 失效
标题翻译：集成电路互连中势垒层的表征
公开(公告)号：US06621290B1
公开(公告)日：2003-09-16
申请号：US09905283
申请日：2001-07-13
申请人： Amit P. Marathe , Pin-Chin Connie Wang
发明人： Amit P. Marathe , Pin-Chin Connie Wang
IPC分类号： G01R3126
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.
摘要翻译：用于测试半导体材料的测试结构和方法设置有具有电接地和电势源的半导体晶片。导体层放置在半导体晶片上方，半导体材料放置在导体层上。介电层放置在半导体材料上。导电顶层和底层放置在电介质层和半导体晶片的底部之上。导电顶层连接到电气接地。导电底层连接到电位源。从导电底层到导电顶层测量电流。

4. 发明授权

US06472757B2 Conductor reservoir volume for integrated circuit interconnects 有权
公开(公告)号：US06472757B2
公开(公告)日：2002-10-29
申请号：US09758994
申请日：2001-01-11
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L23528
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

5. 发明授权

US06455938B1 Integrated circuit interconnect shunt layer 有权
标题翻译：集成电路互连分流层
公开(公告)号：US06455938B1
公开(公告)日：2002-09-24
申请号：US09905479
申请日：2001-07-13
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2945
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.
摘要翻译：提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且第一导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。并联层位于导体芯上方的通孔中。阻挡层将第二通道和通过开口穿过并联层和第二介电层。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。

6. 发明授权

US06417566B1 Void eliminating seed layer and conductor core integrated circuit interconnects 有权
标题翻译：消除种子层和导体芯集成电路互连
公开(公告)号：US06417566B1
公开(公告)日：2002-07-09
申请号：US09705121
申请日：2000-11-01
申请人： Pin-Chin Connie Wang , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76873 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seed layer is disposed between the barrier layer and the conductor core. The seed layer has an associated element which is formed during annealing into an intermetallic compound which has a density lower than the density of the conductor core.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。种子层设置在阻挡层和导体芯之间。种子层具有在退火成形成密度低于导体芯的密度的金属间化合物的相关元件。

7. 发明授权

US06590288B1 Selective deposition in integrated circuit interconnects 有权
标题翻译：集成电路互连中的选择性沉积
公开(公告)号：US06590288B1
公开(公告)日：2003-07-08
申请号：US09874549
申请日：2001-06-04
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/32051 , H01L21/76873 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has an opening formed therein. A first barrier layer is deposited over the first conductor core. A second barrier layer is deposited to line the low dielectric constant dielectric layer and the first barrier layer. A third barrier layer is deposited to line the second barrier layer. A second conductor core is deposited to fill the opening over the third barrier layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。第一导体芯连接到半导体器件。在半导体衬底上形成低介电常数介质层，并且其中形成有开口。第一阻挡层沉积在第一导体芯上。沉积第二阻挡层以对低介电常数介电层和第一阻挡层进行排列。沉积第三阻挡层以使第二阻挡层成线。沉积第二导体芯以填充第三阻挡层上的开口。

8. 发明授权

US06531780B1 Via formation in integrated circuit interconnects 有权
标题翻译：通过集成电路互连形成
公开(公告)号：US06531780B1
公开(公告)日：2003-03-11
申请号：US09894289
申请日：2001-06-27
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76844 , H01L21/76865 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。半导体上的第一通道电介质层具有由第一阻挡层衬里并由第一导体芯填充的第一开口。在第一沟道电介质层上形成具有通向第一导体芯开口的通路开口的通孔电介质层。在通孔电介质层上形成具有对通孔开口的第二开口的第二通道电介质层。第二导体芯填充通孔和第二通道开口。衬在第二导体芯下方的通孔和第二通道开口的第二阻挡层在第二导体芯与通孔和第二通道介电层之间形成阻挡层，但不形成第一和第二导体芯之间的阻挡层。

9. 发明授权

US06649034B1 Electro-chemical metal alloying for semiconductor manufacturing 有权
标题翻译：电化学金属合金化用于半导体制造
公开(公告)号：US06649034B1
公开(公告)日：2003-11-18
申请号：US09894191
申请日：2001-06-27
申请人： Minh Quoc Tran , Amit P. Marathe , Pin-Chin Connie Wang
发明人： Minh Quoc Tran , Amit P. Marathe , Pin-Chin Connie Wang
IPC分类号： C25B1500
CPC分类号： C25D21/14 , C25D3/58
摘要： The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A plurality of consumable remote secondary anodes at different voltages in the plating solution reservoir provides the metal ions for alloy plating.
摘要翻译：本发明提供了一种用于半导体晶片的合金电镀系统，其包括通过循环系统连接到电镀液储存器的电镀室。半导体晶片用作电镀室中具有惰性主阳极的阴极。在电镀溶液储存器中，多个在不同电压下的易消耗的远程次级阳极提供用于合金电镀的金属离子。

10. 发明授权

US06462416B1 Gradated barrier layer in integrated circuit interconnects 有权
标题翻译：集成电路互连中的梯度势垒层
公开(公告)号：US06462416B1
公开(公告)日：2002-10-08
申请号：US09905469
申请日：2001-07-13
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines the opening, the barrier layer having a dielectric layer proximate and distal regions. The barrier layer has no barrier metal adjacent the dielectric layer proximate region and all barrier metal in the dielectric layer distal region, the barrier layer has all barrier compound adjacent the dielectric layer proximate region and no barrier compound before the dielectric layer distal region. A conductor core is over the barrier layer fills the opening and connects to the semiconductor device.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。其中形成有开口的器件介电层形成在半导体衬底上。势垒金属和屏障化合物的阻挡层划分开口，阻挡层具有接近和远端区域的电介质层。阻挡层在电介质层邻近区域附近没有阻挡金属，并且介电层远侧区域中的所有势垒金属，阻挡层具有邻近电介质层邻近区域的所有阻挡化合物，并且在电介质层远端区域之前没有阻挡化合物。阻挡层之上的导体芯填充开口并连接到半导体器件。

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