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    • 1. 发明授权
    • Circuit for testing pumped voltage gates in a programmable gate array
    • 用于在可编程门阵列中测试泵浦电压门的电路
    • US5920201A
    • 1999-07-06
    • US935567
    • 1997-09-23
    • Alok MehrotraCharles R. Erickson
    • Alok MehrotraCharles R. Erickson
    • G01R31/3185G11C29/36G11C29/44G11C29/50G01R27/22
    • G01R31/318519G11C29/44G11C29/36G11C29/50
    • In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.
    • 在现场可编程门阵列中,测试电路用于测试线路的信号路径,通过通过门,并在第二条线路上。 存储单元以VGG电平输出,其中VGG> / = VDD + VTN。 为了动态地测试信号路径,使用三个晶体管和两个测试信号来施加0伏特或者VGG来控制传输门。 两个晶体管耦合到存储单元和通过栅极,而第三晶体管耦合到第一和第二晶体管并接地。 两个测试信号和逆变器控制这些晶体管,使得可以改变存储器状态以根据测试配置动态地切换传递门。 然后通过被测信号路径发送电信号,并监视结果。
    • 3. 发明授权
    • Phase-locked delay loop for clock correction
    • 用于时钟校正的锁相延迟环
    • US5815016A
    • 1998-09-29
    • US665169
    • 1996-06-14
    • Charles R. Erickson
    • Charles R. Erickson
    • G06F1/10H03L7/081H03L7/085H03L7/00H03K5/00
    • G06F1/10H03L7/0812H03L7/085
    • A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.
    • 受控的延迟路径将选定的延迟插入到时钟分配电路中,以创建等于相对于参考停靠信号的整数个时钟周期的总时钟延迟,或者产生与参考停靠信号的选择的相位关系。 本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。 参考时钟信号通过接收参考时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围,并产生一个误差电压,该误差电压调节电压控制的延迟元件以产生输出时钟信号。 可以包括额外的可选择的延迟,其创建偏移选项并且允许选择引导,滞后或同相参考停靠/输出时钟关系。 在一个实施例中,时钟信号的正和负边缘都被校正。 作为另一个特征,如果校正始终在相同的方向上,则产生错误标志。
    • 5. 发明授权
    • Fast pipeline frame full detector
    • 快速管线框架全检测器
    • US5694056A
    • 1997-12-02
    • US627815
    • 1996-04-01
    • John E. MahoneyStephen M. TrimbergerCharles R. Erickson
    • John E. MahoneyStephen M. TrimbergerCharles R. Erickson
    • H03K19/177
    • H03K19/17704
    • A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration data into the IC. Therefore, the present invention advantageously reduces this limiting factor.
    • 一条流水线全检测电路。 本发明可以在使用串行数据流和传送机制将配置数据加载到集成电路(IC)的系统中操作。 对于给定的IC,配置数据以指定大小的连续帧传送到IC。 配置数据的第一位包含一个帧完整指示符。 配置数据被传送到移位寄存器电路中,并且除了存储在移位寄存器电路之外,移位寄存器电路的最后位位置沿特殊帧完整流水线移动到控制单元。 控制单元在检测到帧全指示符时,断言并行写入命令,使得移位寄存器电路的数据被并行地传送到存储器的接收列。 复位信号后,新的配置数据可以被串行移位到相同的移位寄存器电路中。 通过将帧满指示符移动通过流水线,帧全指示器到达控制单元所需的传播延迟显着降低。 正是这种传播延迟将配置数据的传输速率限制在IC中。 因此,本发明有利地减少了这个限制因素。
    • 7. 发明授权
    • Soft wakeup output buffer
    • 软唤醒输出缓冲区
    • US5489858A
    • 1996-02-06
    • US246048
    • 1994-05-19
    • Kerry M. PierceCharles R. Erickson
    • Kerry M. PierceCharles R. Erickson
    • H03K19/173H03K17/16H03K17/687H03K19/003H03K19/0175H03K19/00
    • H03K19/00361
    • Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
    • 当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时,电源或接地电压可能会波动。 特别是在输出缓冲器的全局高阻抗状态释放之后,其中输出信号被被动地驱动到选择的逻辑状态。 为了防止电源和接地电压变化,缓冲器具有用于以慢响应(高偏移)模式操作的装置。 压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。 当转换速率控制电路接收到结束缓冲器的高阻状态的信号时,对该信号施加延迟,并且在延迟时间允许缓冲器移动到快速响应模式之后。 当高电容端子移动到新的逻辑状态时,慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。
    • 8. 发明授权
    • Expert system supported interactive product selection and recommendation
    • 专家系统支持交互式产品选择和推荐
    • US07885820B1
    • 2011-02-08
    • US09909250
    • 2001-07-19
    • Rod MancisidorCharles R. EricksonAhmed GheithWilliam W. Chan
    • Rod MancisidorCharles R. EricksonAhmed GheithWilliam W. Chan
    • G06Q90/00
    • G06N5/04G06Q10/10G06Q30/02
    • Expert system supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
    • 专家系统支持交互式产品选择和推荐。 本发明帮助代理人与客户进行交互,并提供为客户提供可行解决方案的可用产品和/或服务的选择和推荐。 本发明允许使用具有不同技能水平的试剂,包括技能水平较低,而不会产生有害的性能。 从某些角度来看,使用本发明的各个方面的专家系统允许代理人提供与客户的实时交互并为该客户提供实时推荐的解决方案。 处理复杂行业的许多传统方法要求代理人具有高度的技能和专业知识。 本发明甚至允许新手代理服务于客户的需求,而不需要高技能水平或前期训练,这往往是以寻求上市的产品和/或服务为代价的牺牲品。
    • 10. 发明授权
    • Encryption of configuration stream
    • 加密配置流
    • US06212639B1
    • 2001-04-03
    • US09342336
    • 1999-06-29
    • Charles R. EricksonDanesh TavanaVictor A. Holen
    • Charles R. EricksonDanesh TavanaVictor A. Holen
    • H04K100
    • G06F21/57G06F12/1408G06F21/85
    • A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
    • 在可编程逻辑器件(PLD)和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。 该方法包括以下步骤。 将存储在存储设备中的加密配置数据发送到PLD。 解密加密的配置数据以生成PLD中的配置数据的副本。 使用配置数据的副本配置PLD。 在一个实施例中,PLD将密钥发送到存储设备。 在另一个实施例中,密钥分别输入到存储设备和PLD中,并且从未在PLD和存储设备之间传送密钥。 在另一个实施例中,键仅输入到PLD中。 密钥用于加密配置数据。