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1. 发明授权

US06191036B1 Use of photoresist focus exposure matrix array as via etch monitor 失效
标题翻译：使用光刻胶焦点曝光矩阵阵列作为通孔蚀刻监视器
公开(公告)号：US06191036B1
公开(公告)日：2001-02-20
申请号：US09290354
申请日：1999-04-12
申请人： Allen S. Yu , Paul J. Steffan , Bharath Rangarajan
发明人： Allen S. Yu , Paul J. Steffan , Bharath Rangarajan
IPC分类号： H01L21302
CPC分类号： G03F7/70625 , G03F7/70641 , H01L21/76802 , H01L22/34
摘要： A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.
摘要翻译：在半导体制造工艺中预测通孔的蚀刻效能的方法，其中使用光焦点曝光矩阵（FEM）阵列作为通孔蚀刻监视器。 FEM是矩阵阵列，其中每个阵列具有不同大小的通孔集合。阵列中的矩阵的大小大约是晶片中通孔的最小尺寸的两倍，尺寸减小到最小尺寸的一半左右。

2. 发明授权

US06261960B1 High density contacts having rectangular cross-section for dual damascene applications 有权
标题翻译：高密度接触件，具有双镶嵌应用的矩形横截面
公开(公告)号：US06261960B1
公开(公告)日：2001-07-17
申请号：US09545698
申请日：2000-04-06
申请人： Allen S. Yu , Bharath Rangarajan , Paul J. Steffan
发明人： Allen S. Yu , Bharath Rangarajan , Paul J. Steffan
IPC分类号： H01L2100
CPC分类号： H01L21/76816 , H01L21/76802 , H01L21/76807 , H01L21/76811 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination conductive wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities, which are simultaneously filled with a conductive material.
摘要翻译：一种制造在导线和导电通孔之间具有矩形截面界面的半导体器件的方法。对第一层光致抗蚀剂进行图案化以暴露将要形成导线和组合导线和通孔的半导体器件的部分。对第二层光致抗蚀剂进行图案化以暴露将要形成组合导线和通孔的半导体器件的部分。要形成导线的第二层层间电介质和要形成导电通孔的第一层间电介质同时被各向异性地蚀刻以形成同时填充有导电材料的空腔。

3. 发明授权

US06433371B1 Controlled gate length and gate profile semiconductor device 有权
标题翻译：控制栅极长度和栅极配置半导体器件
公开(公告)号：US06433371B1
公开(公告)日：2002-08-13
申请号：US09493428
申请日：2000-01-29
申请人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
发明人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
摘要翻译：提供了超大规模CMOS集成电路半导体器件，其具有具有LDD结构的宽度和轮廓控制的倒梯形门，其具有逐渐的掺杂分布并且用于接触。通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成反向梯形栅极沟槽，在衬底上的反向梯形栅极沟槽中沉积栅极电介质，形成衬底上的结构，从而形成在反向梯形栅极沟槽中的多晶硅栅极，去除栅极层和阻挡层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结，以及制备源极/漏极延伸结和导电连接门。

4. 发明授权

US06430572B1 Recipe management database system 有权
标题翻译：食谱管理数据库系统
公开(公告)号：US06430572B1
公开(公告)日：2002-08-06
申请号：US09264362
申请日：1999-03-08
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1730
CPC分类号： G06F17/30289 , G06F17/30371 , Y10S707/99945 , Y10S707/99948
摘要： A scan tool recipe management database system for recipes utilized in the scanning of semiconductor wafers during the manufacture of the semiconductor wafers. The scan tool recipe management database system includes workstations at each scan tool for simultaneously inputting recipes and changes to the recipes to the scan tool and to a scan tool recipe database.
摘要翻译：一种扫描工具配方管理数据库系统，用于在制造半导体晶片期间在半导体晶片的扫描中使用的配方。扫描工具配方管理数据库系统包括每个扫描工具上的工作站，用于同时输入食谱和对扫描工具和扫描工具配方数据库的配方更改。

5. 发明授权

US06377898B1 Automatic defect classification comparator die selection system 失效
标题翻译：自动缺陷分类比较器模具选择系统
公开(公告)号：US06377898B1
公开(公告)日：2002-04-23
申请号：US09294246
申请日：1999-04-19
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of analyzing and classifying defects on semiconductor wafers during a semiconductor manufacturing process using a comparator die selector system wherein an automatic defect classification review tool compares defects on a die location with an identical location on an identical die. The automatic defect classification review tool locates identical die with information from the comparator die selector system.
摘要翻译：一种在使用比较模片选择系统的半导体制造过程中对半导体晶片上的缺陷进行分析和分类的方法，其中自动缺陷分类评估工具将模具位置上的缺陷与相同模具上的相同位置进行比较。自动缺陷分类检查工具与来自比较器管芯选择器系统的信息定位相同的管芯。

6. 发明授权

US06291252B1 Automatic method to eliminate first-wafer effect 有权
标题翻译：自动消除第一晶圆效应的方法
公开(公告)号：US06291252B1
公开(公告)日：2001-09-18
申请号：US09345175
申请日：1999-06-30
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L2100
CPC分类号： H01L21/67276 , Y10T29/41
摘要： A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafer is automatically processed. If the tool has been on idle beyond the predetermined period of time, a conditioning wafer is automatically processed.
摘要翻译：一种在处理工具中制造半导体晶片的方法，其中确定工具是否已经在预定时间段之后空转。如果工具在预定时间之后没有闲置，则产品晶片被自动处理。如果工具在预定时间段之后已经空转，则调节晶片被自动处理。

7. 发明授权

US06274443B1 Simplified graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极配置的简化分级LDD晶体管
公开(公告)号：US06274443B1
公开(公告)日：2001-08-14
申请号：US09162116
申请日：1998-09-28
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28123 , H01L21/823814 , H01L29/665 , H01L29/6659
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.
摘要翻译：通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以使所得到的LDD结构远离所述第二多晶硅的边缘随后将形成具有基本垂直轮廓的多晶硅栅极。由于LDD结构与第二多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减小。

8. 发明授权

US06239008B1 Method of making a density multiplier for semiconductor device manufacturing 有权
标题翻译：制造用于半导体器件制造的密度倍增器的方法
公开(公告)号：US06239008B1
公开(公告)日：2001-05-29
申请号：US09407907
申请日：1999-09-29
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L213205
CPC分类号： H01L21/3081 , H01L21/0274 , H01L21/0277 , H01L21/0278 , H01L21/0332
摘要： A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.
摘要翻译：制造具有比制造工艺中使用的光刻系统所提供的尺寸小至少一个尺寸的结构密度增加的半导体器件的方法。

9. 发明授权

US5985753A Method to manufacture dual damascene using a phantom implant mask 有权
标题翻译：使用幻影植入物掩模制造双镶嵌的方法
公开(公告)号：US5985753A
公开(公告)日：1999-11-16
申请号：US136866
申请日：1998-08-19
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/0337 , H01L21/31144 , H01L21/7681 , H01L21/76813 , H01L2221/1026
摘要： Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.
摘要翻译：制造半导体器件的方法，其中所选择的层以具有要形成在第一层间电介质层中的通孔结构的尺寸的图案中注入重离子。在第一实施例中，将离子注入形成在第一和第二层间电介质层之间的蚀刻停止层中。在第二实施例中，将离子注入第二层间电介质层。选择性蚀刻工艺在第二层间电介质层中形成沟槽结构，并在第一层间电介质层中形成通孔结构。通孔结构和沟槽结构填充有导电材料。

10. 发明授权

US06424881B1 Computer generated recipe selector utilizing defect file information 有权
标题翻译：计算机生成的配方选择器利用缺陷文件信息
公开(公告)号：US06424881B1
公开(公告)日：2002-07-23
申请号：US09404081
申请日：1999-09-23
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing semiconductor devices wherein a computer generated list of appropriate review recipes for each layer is available to be used by a review station to review defects on each layer. The most appropriate review recipe is used by the review station unless a review station operator selects an alternate review recipe.
摘要翻译：一种制造半导体器件的方法，其中计算机产生的每个层的适当的审查配方的列表可被审查站用于审查每个层上的缺陷。审查站使用最合适的审查方法，除非审查站操作员选择备用审查配方。

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