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1. 发明申请

US20130246737A1 SIMD Compare Instruction Using Permute Logic for Distributed Register Files 有权
标题翻译： SIMD比较指令使用分布式寄存器文件的权限逻辑
公开(公告)号：US20130246737A1
公开(公告)日：2013-09-19
申请号：US13420699
申请日：2012-03-15
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/3838
摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
摘要翻译：提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。基于该结果，SIMD处理器可以执行各种操作。

2. 发明授权

US09575753B2 SIMD compare instruction using permute logic for distributed register files 有权
标题翻译： SIMD比较指令使用分布式寄存器文件的置换逻辑
公开(公告)号：US09575753B2
公开(公告)日：2017-02-21
申请号：US13420699
申请日：2012-03-15
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/3838
摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
摘要翻译：提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。基于该结果，SIMD处理器可以执行各种操作。

3. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明申请

US20100095087A1 Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture 有权
标题翻译：浮点数SIMD架构中动态数据驱动对齐和数据格式化
公开(公告)号：US20100095087A1
公开(公告)日：2010-04-15
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/06
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.
摘要翻译：为浮点SIMD架构提供动态数据驱动对齐和数据格式化的机制。至少两个操作数输入被输入到处理器的置换单元。每个操作数输入包含至少一个浮点值，在该浮点值上由置换单元执行置换操作。具有一起构成控制向量输入的多个浮点值的控制矢量输入被输入到处理器的置换单元，用于控制置换单元的置换操作。置换单元根据由构成控制向量输入的多个浮点值指定的置换模式对至少两个操作数输入执行置换操作。此外，置换操作的结果输出从处理单元输出到处理器的结果向量寄存器。

5. 发明申请

US20100095086A1 Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors 失效
标题翻译：基于与精简向量精简对应的地址动态对齐增强精度向量
公开(公告)号：US20100095086A1
公开(公告)日：2010-04-15
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

6. 发明授权

US09652231B2 All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture 有权
公开(公告)号：US09652231B2
公开(公告)日：2017-05-16
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/315 , G06F7/76 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.

7. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

8. 发明授权

US07865693B2 Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type 失效
标题翻译：使用指示相对于精度类型的元素边界的偏移的掩码对齐精确转换的矢量数据
公开(公告)号：US07865693B2
公开(公告)日：2011-01-04
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/16
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

9. 发明授权

US09223580B2 Systems, methods and computer products for cross-thread scheduling 有权
标题翻译：用于跨线程调度的系统，方法和计算机产品
公开(公告)号：US09223580B2
公开(公告)日：2015-12-29
申请号：US11847556
申请日：2007-08-30
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A Gunnels , James L. McInnes , Mark P. Mendell
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A Gunnels , James L. McInnes , Mark P. Mendell
IPC分类号： G06F9/455 , G06F9/46 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3851 , G06F8/445 , G06F9/3885
摘要： Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.
摘要翻译：用于跨线程调度的系统，方法和计算机产品。示例性实施例包括用于编译代码的交叉线程调度方法，所述方法包括：响应于所述调度单元处于所述代码的非多线程部分中的调度器子操作来调度调度单元，并且调度所述调度单元，响应于调度单元处于代码的多线程部分中的线程调度器子操作。

10. 发明授权

US08954943B2 Analyze and reduce number of data reordering operations in SIMD code 有权
标题翻译：分析和减少SIMD代码中数据重排序的数量
公开(公告)号：US08954943B2
公开(公告)日：2015-02-10
申请号：US11340452
申请日：2006-01-26
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
IPC分类号： G06F9/45 , G06F15/00 , G06F15/76
CPC分类号： G06F8/443
摘要： A method for analyzing data reordering operations in Single Issue Multiple Data source code and generating executable code therefrom is provided. Input is received. One or more data reordering operations in the input are identified and each data reordering operation in the input is abstracted into a corresponding virtual shuffle operation so that each virtual shuffle operation forms part of an expression tree. One or more virtual shuffle trees are collapsed by combining virtual shuffle operations within at least one of the one or more virtual shuffle trees to form one or more combined virtual shuffle operations, wherein each virtual shuffle tree is a subtree of the expression tree that only contains virtual shuffle operations. Then code is generated for the one or more combined virtual shuffle operations.
摘要翻译：提供了一种用于分析单发多数据源代码中的数据重排序操作并从中生成可执行代码的方法。收到输入。识别输入中的一个或多个数据重排序操作，并将输入中的每个数据重排序操作抽象为相应的虚拟随机播放操作，使得每个虚拟随机播放操作形成表达式树的一部分。通过将所述一个或多个虚拟随机播放树中的至少一个中的虚拟随机播放操作组合以形成一个或多个组合的虚拟随机播放操作来折叠一个或多个虚拟洗牌树，其中每个虚拟随机播放树是仅包含表达式树的子树虚拟随机操作。然后为一个或多个组合的虚拟随机操作生成代码。

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