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1. 发明授权

US07710952B1 Flexible counter update and retrieval 有权
标题翻译：灵活的计数器更新和检索
公开(公告)号：US07710952B1
公开(公告)日：2010-05-04
申请号：US11943225
申请日：2007-11-20
申请人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
发明人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
IPC分类号： H04Q11/00
CPC分类号： H04L49/30
摘要： A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.
摘要翻译：网络设备包括一个或多个处理单元和外部存储器。一个或多个处理单元中的每一个包括被配置为对相应的处理单元进行计费的集中式计数器。所述外部存储器与所述一个或多个处理单元中的至少一个相关联，并且被配置为存储所述至少一个处理单元的一组计数值。

2. 发明授权

US07317718B1 Flexible counter update and retrieval 有权
标题翻译：灵活的计数器更新和检索
公开(公告)号：US07317718B1
公开(公告)日：2008-01-08
申请号：US10310778
申请日：2002-12-06
申请人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
发明人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
IPC分类号： H04Q11/00
CPC分类号： H04L49/30
摘要： A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.
摘要翻译：网络设备包括一个或多个处理单元和外部存储器。一个或多个处理单元中的每一个包括被配置为对相应的处理单元进行计费的集中式计数器。所述外部存储器与所述一个或多个处理单元中的至少一个相关联，并且被配置为存储所述至少一个处理单元的一组计数值。

3. 发明授权

US08331359B2 Flexible counter update and retrieval 有权
标题翻译：灵活的计数器更新和检索
公开(公告)号：US08331359B2
公开(公告)日：2012-12-11
申请号：US12723280
申请日：2010-03-12
申请人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
发明人： Albert Weichung Kuo , Reuven Meyer Samuel , Debashis Basu , Arunachalam Vaidyanathan , Spencer Greene
IPC分类号： H04Q11/00
CPC分类号： H04L49/30
摘要： A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.
摘要翻译：网络设备包括一个或多个处理单元和外部存储器。一个或多个处理单元中的每一个包括被配置为对相应的处理单元进行计费的集中式计数器。所述外部存储器与所述一个或多个处理单元中的至少一个相关联，并且被配置为存储所述至少一个处理单元的一组计数值。

4. 发明授权

US5905885A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
标题翻译：用于连接多种格式的外围设备和单个系统总线的方法和装置
公开(公告)号：US5905885A
公开(公告)日：1999-05-18
申请号：US933884
申请日：1997-09-19
申请人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
发明人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
IPC分类号： G06F13/38 , G06F13/10 , G06F5/01
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.
摘要翻译：被称为系统适配器和插座控制器的包括一对集成电路的外围接口系统和设备使用称为窗口 - 芯片间通信协议的通信协议来接口诸如PCMCIA卡或红外线设备和具有CPU系统总线的具有不同格式的其他子系统。系统适配器使用ATA通信标准与硬盘驱动器子系统进行通信，以将ATA硬盘驱动器与CPU系统总线进行接口。与PCMCIA外设卡和IR外围设备通信的系统适配器和插座控制器之间的通信使用可与其他通信协议共享硬件资源的窗口 - 芯片间通信协议实现。系统适配器和硬盘驱动器之间以及系统适配器和插座控制器之间的通信可以提供在标准40信号带状电缆的同一链上。备选地，扩展板和插座控制器之间的通信可以与具有不同信号线格式的硬盘驱动器分离的电缆进行。系统适配器可以包括在可以连接到主板和CPU系统总线的单个接口扩展板中，或者可以直接连接或焊接到主板，并使用一个或多个总线与插座控制器和ATA硬盘驱动器进行通信。

5. 发明授权

US5594874A Automatic bus setting, sensing and switching interface unit 失效
标题翻译：自动总线设置，感测和切换接口单元
公开(公告)号：US5594874A
公开(公告)日：1997-01-14
申请号：US130090
申请日：1993-09-30
申请人： Puducode S. Narayanan , Tai T. Nguyen , Arunachalam Vaidyanathan , Edward C. Garcia
发明人： Puducode S. Narayanan , Tai T. Nguyen , Arunachalam Vaidyanathan , Edward C. Garcia
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4072
摘要： An integrated automatic bus setting, sensing and switching interface unit is manufactured on board an integrated circuit to interface between the integrated circuit and the system bus. The interface unit can support a plurality of bus structures utilizing the same pins on the integrated circuit for different functions. Several modes of establishing an interface structure are available in the unit. An Address Strobe pin on the integrated circuit is used to automatically detect a signal level representative of the bus structure to be used. A code representative of the parameters of the bus structure is also stored in a configuration register for controlling the interface unit and configuring the pins on the integrated circuit for the specific bus structure to be used. The Basic Input Output System (BIOS) as its first operation stores the code in a register whose contents are then written to the configuration register of the integrated circuit for controlling and configuring the integrated circuit. A combination of these modes is also available.
摘要翻译：集成自动总线设置，感测和切换接口单元在集成电路上制造，以在集成电路和系统总线之间进行接口。接口单元可以支持使用集成电路上相同引脚的多个总线结构，用于不同的功能。建立界面结构的几种模式在本单元中可用。集成电路上的地址选通引脚用于自动检测代表要使用的总线结构的信号电平。代表总线结构参数的代码也存储在配置寄存器中，用于控制接口单元并配置用于要使用的特定总线结构的集成电路上的引脚。基本输入输出系统（BIOS）作为其第一操作将代码存储在寄存器中，其内容然后被写入用于控制和配置集成电路的集成电路的配置寄存器。这些模式的组合也是可用的。

6. 发明授权

US5812858A Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同集成电路之间提供寄存器和中断兼容性的方法和装置
公开(公告)号：US5812858A
公开(公告)日：1998-09-22
申请号：US719596
申请日：1996-09-25
申请人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
发明人： Narasimha R. Nookala , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Jihad Y. Abudayyeh , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F13/10 , G06F9/46
CPC分类号： G06F13/105 , G06F9/30098 , G06F9/30123 , G06F9/30189 , G06F9/455
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的设备被设计为使用为先前硬件编写的软件进行操作。为先前硬件编写的软件版本尝试非本地寄存器访问，集成电路设计用于模拟非本地寄存器集。针对当前硬件专门编写的软件版本会尝试不需要仿真的本地寄存器访问。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，中断信息被写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。在第一和第二模式中，来自适当寄存器的转向位用于将系统，管理和唤醒中断映射到中断请求信号然后成形的适当中断焊盘。

7. 发明授权

US5796981A Method and apparatus for providing register compatibility between non-identical integrated circuits 失效
标题翻译：用于在不相同的集成电路之间提供寄存器兼容性的方法和装置
公开(公告)号：US5796981A
公开(公告)日：1998-08-18
申请号：US308167
申请日：1994-09-16
申请人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
发明人： Jihad Y. Abudayyeh , Ashutosh S. Dikshit , Daniel G. Bezzant , Stephen A. Smith , Narasimha R. Nookala , Arunachalam Vaidyanathan
IPC分类号： G06F9/30 , G06F9/318 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30174 , G06F9/30138
摘要： An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.
摘要翻译：用于在具有不同寄存器和中断配置的集成电路之间提供寄存器兼容性的装置被设计为与软件一起操作。软件可以尝试非本地寄存器访问; 本发明的集成电路将模拟非本地寄存器组。在优选实施例中，集成电路中仅包括一个物理寄存器组，并且当尝试非本地寄存器访问时使用兼容性引擎。兼容性引擎耦合在总线接口单元和物理寄存器组之间，并且允许用户或系统设计者寻址具有与物理寄存器组不同的配置的另一个集成电路的寄存器组。兼容性引擎转换地址，并将仿真寄存器的数据位映射到物理寄存器集中的寄存器。或者，集成电路可以物理地包括两组寄存器。中断兼容性电路还被设计为在至少第一模式或第二模式中操作。在第一种模式下，将中断信息写入适当的寄存器，然后映射到物理寄存器组的相应位。在第二种模式下，中断信息直接写入适当的寄存器。

8. 发明授权

US5727184A Method and apparatus for interfacing between peripherals of multiple formats and a single system bus 失效
公开(公告)号：US5727184A
公开(公告)日：1998-03-10
申请号：US266975
申请日：1994-06-27
申请人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
发明人： Bryan M. Richter , Stephen A. Smith , Daniel G. Bezzant , Kasturiraman Gopalaswamy , Suhas Anand Shetty , Arunachalam Vaidyanathan
IPC分类号： G06F13/38 , G06F13/10 , G06F5/01
CPC分类号： G06F13/385
摘要： A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

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