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1. 发明授权

US5677869A Programming flash memory using strict ordering of states 失效
标题翻译：使用严格的状态排序编程闪存
公开(公告)号：US5677869A
公开(公告)日：1997-10-14
申请号：US572730
申请日：1995-12-14
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi , Paul Ruby
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi , Paul Ruby
IPC分类号： G11C11/56 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642 , G11C2211/5647
摘要： A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.
摘要翻译：一种用于编程存储器单元阵列的方法，其中每个单元可以被放置在两个以上的状态。该方法包括以下步骤：1）选择多个不同的编程电压电平，其中每个编程电压电平与多个状态中的相应一个状态相关联，以及2）将多个编程脉冲施加到存储器阵列的选定子集单元，其中每个编程脉冲具有编程电压电平之一和相应的多个脉冲宽度中的一个，使得所选择的子集中的相应一个的每个存储器单元被直接编程为多个状态中的相应一个状态，通过相应的编程脉冲。

2. 发明授权

US5892710A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5892710A
公开(公告)日：1999-04-06
申请号：US910866
申请日：1997-08-13
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C16/04
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

3. 发明授权

US6091618A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
标题翻译：用于在单个存储元件中存储离散量的电荷的方法和电路
公开(公告)号：US6091618A
公开(公告)日：2000-07-18
申请号：US910761
申请日：1997-08-13
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C13/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.
摘要翻译：一种用于将存储器单元编程为至少三个电荷量之一的方法和电路。通过增加施加到存储单元的编程脉冲的电压电平来增加放置在存储单元中的电荷量。

4. 发明授权

US5566125A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5566125A
公开(公告)日：1996-10-15
申请号：US422066
申请日：1995-03-31
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C13/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

5. 发明授权

US5440505A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5440505A
公开(公告)日：1995-08-08
申请号：US185187
申请日：1994-01-21
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C11/40
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

6. 发明授权

US5402370A Circuitry and method for selecting a drain programming voltage for a nonvolatile memory 失效
标题翻译：用于选择非易失性存储器的漏极编程电压的电路和方法
公开(公告)号：US5402370A
公开(公告)日：1995-03-28
申请号：US119738
申请日：1993-09-10
申请人： Albert Fazio , Gregory E. Atwood , James Brennan, Jr. , Marc E. Landgraf
发明人： Albert Fazio , Gregory E. Atwood , James Brennan, Jr. , Marc E. Landgraf
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/30 , G11C16/34 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C29/021 , G11C16/30 , G11C16/34 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C16/04 , G11C2029/5004
摘要： A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time. A method for setting the drain programming voltage for the nonvolatile memory such that the drain programming voltage varies inversely with respect to the programming ability of the nonvolatile memory is also described.
摘要翻译：描述驻留在单个基板上的非易失性存储器。非易失性存储器包括具有至少存储单元的存储器阵列。存储单元包括漏极区域，源极区域，控制栅极和浮动栅极。漏极编程电压产生电路耦合到编程电压源和存储单元的漏极区域，用于在存储器单元的编程期间向漏极区域提供漏极编程电压。控制电路耦合到漏极编程电压产生电路，用于使漏极编程电压相对于存储器单元的编程能力而变化，使得存储器单元被编程在预定阈值电压的预定范围内，其中预定的编程电压用于预定的编程时间。还描述了一种用于设置非易失性存储器的漏极编程电压的方法，使得漏极编程电压相对于非易失性存储器的编程能力反向变化。

7. 发明授权

US5729489A Programming flash memory using predictive learning methods 失效
标题翻译：使用预测学习方法编程闪存
公开(公告)号：US5729489A
公开(公告)日：1998-03-17
申请号：US572757
申请日：1995-12-14
申请人： Albert Fazio , Gregory E. Atwood , James O. Mi , Paul Ruby
发明人： Albert Fazio , Gregory E. Atwood , James O. Mi , Paul Ruby
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C2211/5625
摘要： A method for programming a memory cell having more than two possible states to a desired state. The method includes applying a programming pulse to the memory cell. The change in the amount of charge stored by the memory cell caused by applying the programming pulse to the memory cell is sensed. The control engine determines characterization information indicative of programming characteristics of the memory cell in response to the detected change in the amount of charge stored by the memory cell. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.
摘要翻译：一种用于将具有多于两种可能状态的存储单元编程到期望状态的方法。该方法包括将编程脉冲施加到存储器单元。感测到通过将编程脉冲施加到存储单元而由存储单元存储的电荷量的变化。控制引擎响应于检测到的由存储器单元存储的电荷量的变化来确定指示存储器单元的编程特性的表征信息。控制引擎然后使用表征信息直接将存储器单元编程到大致期望的状态，而不执行程序验证操作。

8. 发明授权

US5508958A Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage 失效
标题翻译：通过施加可变栅极电压来感测浮置栅极存储单元的状态的方法和装置
公开(公告)号：US5508958A
公开(公告)日：1996-04-16
申请号：US315292
申请日：1994-09-29
申请人： Albert Fazio , Gregory E. Atwood , Mark E. Bauer
发明人： Albert Fazio , Gregory E. Atwood , Mark E. Bauer
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C27/00 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C27/005 , G11C2211/5634 , G11C2211/5642 , G11C2211/5644 , G11C7/16
摘要： A method and apparatus for sensing the state of floating gate memory cells in a memory array. Because of its stability and accuracy, the sensing apparatus may be used for sensing the state of multi-bit floating gate memory cells. The state of a memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage. For another embodiment, a digital-to-analog converter is used to generate the variable gate voltage. A counter generates digital values to step the variable gate voltage. When the cell current equals the fixed reference current, the digital counter value is latched to indicate the state of the memory cell.
摘要翻译：一种用于感测存储器阵列中的浮动栅极存储器单元的状态的方法和装置。由于其稳定性和精度，感测装置可以用于感测多位浮动栅极存储单元的状态。通过向浮动栅极存储单元的顶栅施加可变栅极电压并将单元电流与固定参考电流进行比较来感测存储单元的状态。电路检测电池电流何时等于参考电流。当电流相等时，可变栅极电压的值表示存储单元的状态。对于一个实施例，模数转换器将可变栅极电压转换成当电流相等时被锁存的数字值。锁存的数字值表示存储单元的状态。对于该实施例，可以使用斜坡电压或其它合适的可变电压作为可变栅极电压。对于另一个实施例，使用数模转换器来产生可变栅极电压。一个计数器产生数字值，以步进可变栅极电压。当单元电流等于固定参考电流时，数字计数器值被锁存以指示存储单元的状态。

9. 发明授权

US5239505A Floating gate non-volatile memory with blocks and memory refresh 失效
标题翻译：浮动门非易失性存储器与块和内存刷新
公开(公告)号：US5239505A
公开(公告)日：1993-08-24
申请号：US635308
申请日：1990-12-28
申请人： Albert Fazio , Gregory E. Atwood , Neal R. Mielke
发明人： Albert Fazio , Gregory E. Atwood , Neal R. Mielke
IPC分类号： G11C16/28 , G11C16/34
CPC分类号： G11C16/3431 , G11C16/28 , G11C16/3418
摘要： A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. The second block includes a second memory cell having a drain region, a source region, a floating gate, and a control gate. A second word line is coupled to the control gate of the second memory cell. A bit line is coupled to the drain region of the first and the second memory cell. A refresh control means performs a refresh operation on one of the first and second memory cell. A sensing means is coupled to the bit line, and has a first reference potential and a second reference potential for detecting a voltage state of the first and second memory cell during the refresh operation. When the voltage state is detected to fall between the first reference potential and the second reference potential, the sensing means generates a refresh signal to the refresh control means. When the refresh control means receives the refresh signal from the sensing means, the voltage state is raised above the second reference potential. A method of refreshing the non-volatile device is also described.
摘要翻译：描述非易失性存储器件。存储器件包括第一块和第二块。第一块包括具有漏极区域，源极区域，浮动栅极和控制栅极的第一存储单元。第一字线耦合到第一存储器单元的控制栅极。第二块包括具有漏极区域，源极区域，浮动栅极和控制栅极的第二存储单元。第二字线耦合到第二存储单元的控制栅极。位线耦合到第一和第二存储单元的漏极区域。刷新控制装置对第一和第二存储单元之一执行刷新操作。感测装置耦合到位线，并且具有用于在刷新操作期间检测第一和第二存储器单元的电压状态的第一参考电位和第二参考电位。当检测到电压状态落在第一参考电位和第二参考电位之间时，感测装置向刷新控制装置产生刷新信号。当刷新控制装置从感测装置接收到刷新信号时，电压状态升高到高于第二参考电位。还描述了刷新非易失性设备的方法。

10. 发明授权

US5546042A High precision voltage regulation circuit for programming multiple bit flash memory 失效
标题翻译：用于编程多位闪存的高精度电压调节电路
公开(公告)号：US5546042A
公开(公告)日：1996-08-13
申请号：US423558
申请日：1995-04-17
申请人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Wojciechowski
发明人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Wojciechowski
IPC分类号： G05F1/46 , G11C5/14 , G11C11/56 , G11C16/30 , G05F1/613
CPC分类号： G11C11/5621 , G05F1/465 , G11C16/30 , G11C5/147
摘要： A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.
摘要翻译：一种电压调节电路，包括用于对输入电压进行采样并保持响应于输入电压而产生的参考电压的采样和保持电路。采样和保持电路包括保持参考电压的电容器。电压调节电路还包括耦合到采样和保持电路的电容器的调节器电路。调节器电路使用由电容器提供的参考电压输出输出电压。电压调节电路可用于提供用于对具有两个或多个模拟状态的存储器单元进行编程的高精度编程电压。

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