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1. 发明授权

US5801991A Deselected word line that floats during MLC programming of a flash memory 失效
标题翻译：取消选择的字线，在闪存的MLC编程期间浮动
公开(公告)号：US5801991A
公开(公告)日：1998-09-01
申请号：US829245
申请日：1997-03-31
申请人： Stephen N. Keeney , Albert Fazio , Ken Wojciechowski , Mark Bauer
发明人： Stephen N. Keeney , Albert Fazio , Ken Wojciechowski , Mark Bauer
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/10 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C8/08 , G11C8/10 , G11C16/08 , G11C8/14
摘要： A method of programming a flash memory cell. The method occurs in a memory device having a decoder that receives a select signal. The decoder is coupled to a first word line and a second word line. The first word line is coupled to a first memory cell and the second word line is coupled to a second memory cell. The select signal is asserted to a first voltage such that the decoder selects the first word line and the first memory cell and deselects the second word line and the second memory cell. The select signal is then asserted to a second voltage such that the decoder couples a programming voltage to the first word line and floats the second word line. The first memory cell is then programmed while the second word line is floating.
摘要翻译：闪存单元编程方法。该方法发生在具有接收选择信号的解码器的存储器件中。解码器耦合到第一字线和第二字线。第一字线耦合到第一存储器单元，第二字线耦合到第二存储器单元。选择信号被确定为第一电压，使得解码器选择第一字线和第一存储器单元，并且取消选择第二字线和第二存储器单元。然后，选择信号被确定为第二电压，使得解码器将编程电压耦合到第一字线并浮置第二字线。然后第一个存储单元被编程，而第二个字线是浮动的。

2. 发明授权

US06697282B1 Reference voltage generator employing large flash memory cells coupled to threshold tuning devices 失效
标题翻译：采用耦合到阈值调谐装置的大型闪存单元的参考电压发生器
公开(公告)号：US06697282B1
公开(公告)日：2004-02-24
申请号：US09676583
申请日：2000-09-29
申请人： Stephen N. Keeney , Kerry D. Tedrow , Krishna Kumar Parat
发明人： Stephen N. Keeney , Kerry D. Tedrow , Krishna Kumar Parat
IPC分类号： G11C1628
CPC分类号： G11C16/28
摘要： A reference voltage generator for a flash memory is described. Specifically, the memory cells used in implementing a reference voltage generator are increased in size to enable the generator to be less sensitive to temperature changes as well as device noise. The flash cells may be coupled to threshold tuning devices, which enable the threshold voltage to be easily trimmed.
摘要翻译：描述了用于闪速存储器的参考电压发生器。具体地说，用于实现参考电压发生器的存储单元的尺寸增加，使得发生器对温度变化以及器件噪声不太敏感。闪存单元可以耦合到阈值调谐装置，这使得能够容易地修剪阈值电压。

3. 发明授权

US5798966A Flash memory VDS compensation techiques to reduce programming variability 失效
标题翻译：闪存VDS补偿技术，以减少编程变异性
公开(公告)号：US5798966A
公开(公告)日：1998-08-25
申请号：US828873
申请日：1997-03-31
申请人： Stephen N. Keeney
发明人： Stephen N. Keeney
IPC分类号： G11C16/06 , G11C16/10 , G11C16/30 , G11C11/34
CPC分类号： G11C16/10 , G11C16/30
摘要： A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.
摘要翻译：非易失性存储器件。对于一个实施例，非易失性存储器件包括位线，源极线和具有耦合到位线的漏极的非易失性存储器单元，耦合到源极线的源极，控制栅极和浮置栅极。非易失性存储器件还包括耦合到源极线的源极电压发生器电路，并且在编程非易失性存储器单元时产生源极线电压。源电压发生器电路基于存储器阵列中的非易失性存储单元的位置来改变源极线电压。非易失性存储器件还可以包括耦合到位线的漏极电压发生器电路，并且在编程非易失性存储器单元时产生位线电压。漏极电压发生器电路基于存储器阵列中的非易失性存储器单元的位置改变位线电压。

4. 发明授权

US06462990B1 Post erase repair to enhance performance in a flash memory 失效
标题翻译：擦除擦除功能以提高闪存中的性能
公开(公告)号：US06462990B1
公开(公告)日：2002-10-08
申请号：US09752197
申请日：2000-12-29
申请人： Stephen N. Keeney
发明人： Stephen N. Keeney
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A technique of performing post erase repair on a flash memory by identifying a leaky column after the flash memory is erased. The leaky column is repaired first by programming memory cells of the column to increase the threshold voltage Vt of the memory cells to remove the leaky column condition prior to performing post erase repair on the memory cells. Then, each memory cell is verified and repaired to ensure that each memory cell has a Vt above an acceptable post erase repair value. By performing the column leakage repair first, over erased leakage from deselected cells are not present to give false indications when each cell is verified for the post erase repair Vt.
摘要翻译：通过在擦除闪速存储器之后识别泄漏列来在闪存上执行擦除后修复的技术。首先通过对列的存储单元进行编程来修复泄漏柱，以在对存储器单元执行擦除后修复之前增加存储器单元的阈值电压Vt以消除泄漏列条件。然后，对每个存储单元进行验证和修复，以确保每个存储单元的Vt高于可接受的擦除后修复值。通过首先执行色谱柱泄漏修复，当每个单元格被验证用于擦除后修复Vt时，不存在未被选择的单元的擦除的泄漏以给出错误的指示。

5. 发明授权

US5553020A Structure and method for low current programming of flash EEPROMs 失效
标题翻译：闪存EEPROM低电流编程的结构和方法
公开(公告)号：US5553020A
公开(公告)日：1996-09-03
申请号：US521656
申请日：1995-08-31
申请人： Stephen N. Keeney , Gregory E. Atwood
发明人： Stephen N. Keeney , Gregory E. Atwood
IPC分类号： G11C11/56 , G11C16/10 , H01L27/115 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C2211/5622 , G11C2211/565 , H01L27/115
摘要： A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.
摘要翻译：用于编程非易失性存储器的系统和方法可实现快速的低电流编程。通过施加源偏置电压并将漏极电压增加到大于源极偏置电压来维持快速编程，可实现低电流编程。此外，对于MLC应用，控制栅极电压可以从最小值阶跃或斜坡化以进一步降低峰值通道电流并允许将闪存单元阈值电压置于精确值。可以独立地或结合施加的源偏置电压来完成控制栅极的斜坡或步进。此外，降低的电池电流允许并行编程更多的单元，这提高了程序性能，并且可以减小漏极选择器件的尺寸以减小管芯面积。

6. 发明授权

US5546042A High precision voltage regulation circuit for programming multiple bit flash memory 失效
标题翻译：用于编程多位闪存的高精度电压调节电路
公开(公告)号：US5546042A
公开(公告)日：1996-08-13
申请号：US423558
申请日：1995-04-17
申请人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Wojciechowski
发明人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Wojciechowski
IPC分类号： G05F1/46 , G11C5/14 , G11C11/56 , G11C16/30 , G05F1/613
CPC分类号： G11C11/5621 , G05F1/465 , G11C16/30 , G11C5/147
摘要： A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.
摘要翻译：一种电压调节电路，包括用于对输入电压进行采样并保持响应于输入电压而产生的参考电压的采样和保持电路。采样和保持电路包括保持参考电压的电容器。电压调节电路还包括耦合到采样和保持电路的电容器的调节器电路。调节器电路使用由电容器提供的参考电压输出输出电压。电压调节电路可用于提供用于对具有两个或多个模拟状态的存储器单元进行编程的高精度编程电压。

7. 发明授权

US5497119A High precision voltage regulation circuit for programming multilevel flash memory 失效
标题翻译：用于编程多级闪存的高精度电压调节电路
公开(公告)号：US5497119A
公开(公告)日：1996-03-05
申请号：US252585
申请日：1994-06-01
申请人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Woiciechowski
发明人： Kerry D. Tedrow , Stephen N. Keeney , Albert Fazio , Gregory E. Atwood , Johnny Javanifard , Kenneth Woiciechowski
IPC分类号： G05F1/46 , G11C5/14 , G11C11/56 , G11C16/30 , G05F1/10 , H03K3/02
CPC分类号： G11C11/5621 , G05F1/465 , G11C16/30 , G11C5/147
摘要： A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.
摘要翻译：一种电压调节电路，包括用于对输入电压进行采样并保持响应于输入电压而产生的参考电压的采样和保持电路。采样和保持电路包括保持参考电压的电容器。电压调节电路还包括耦合到采样和保持电路的电容器的调节器电路。调节器电路使用由电容器提供的参考电压输出输出电压。电压调节电路可用于提供用于对具有两个或多个模拟状态的存储器单元进行编程的高精度编程电压。

8. 发明授权

US5487033A Structure and method for low current programming of flash EEPROMS 失效
标题翻译：闪存EEPROM的低电流编程的结构和方法
公开(公告)号：US5487033A
公开(公告)日：1996-01-23
申请号：US267815
申请日：1994-06-28
申请人： Stephen N. Keeney , Gregory E. Atwood
发明人： Stephen N. Keeney , Gregory E. Atwood
IPC分类号： G11C11/56 , G11C16/10 , H01L27/115 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C2211/5622 , G11C2211/565 , H01L27/115
摘要： A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.
摘要翻译：用于编程非易失性存储器的系统和方法可实现快速的低电流编程。通过施加源偏置电压并将漏极电压增加到大于源极偏置电压来维持快速编程，可实现低电流编程。此外，对于MLC应用，控制栅极电压可以从最小值阶跃或斜坡化以进一步降低峰值通道电流并允许将闪存单元阈值电压置于精确值。可以独立地或结合施加的源偏置电压来完成控制栅极的斜坡或步进。此外，降低的电池电流允许并行编程更多的单元，这提高了程序性能，并且可以减小漏极选择器件的尺寸以减小管芯面积。

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