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1. 发明授权

US5677869A Programming flash memory using strict ordering of states 失效
标题翻译：使用严格的状态排序编程闪存
公开(公告)号：US5677869A
公开(公告)日：1997-10-14
申请号：US572730
申请日：1995-12-14
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi , Paul Ruby
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi , Paul Ruby
IPC分类号： G11C11/56 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642 , G11C2211/5647
摘要： A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.
摘要翻译：一种用于编程存储器单元阵列的方法，其中每个单元可以被放置在两个以上的状态。该方法包括以下步骤：1）选择多个不同的编程电压电平，其中每个编程电压电平与多个状态中的相应一个状态相关联，以及2）将多个编程脉冲施加到存储器阵列的选定子集单元，其中每个编程脉冲具有编程电压电平之一和相应的多个脉冲宽度中的一个，使得所选择的子集中的相应一个的每个存储器单元被直接编程为多个状态中的相应一个状态，通过相应的编程脉冲。

2. 发明授权

US5892710A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5892710A
公开(公告)日：1999-04-06
申请号：US910866
申请日：1997-08-13
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C16/04
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

3. 发明授权

US5566125A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5566125A
公开(公告)日：1996-10-15
申请号：US422066
申请日：1995-03-31
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C13/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

4. 发明授权

US5440505A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5440505A
公开(公告)日：1995-08-08
申请号：US185187
申请日：1994-01-21
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C11/40
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

5. 发明授权

US6091618A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
标题翻译：用于在单个存储元件中存储离散量的电荷的方法和电路
公开(公告)号：US6091618A
公开(公告)日：2000-07-18
申请号：US910761
申请日：1997-08-13
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C13/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.
摘要翻译：一种用于将存储器单元编程为至少三个电荷量之一的方法和电路。通过增加施加到存储单元的编程脉冲的电压电平来增加放置在存储单元中的电荷量。

6. 发明授权

US07743412B1 Computer system identification 失效
标题翻译：计算机系统识别
公开(公告)号：US07743412B1
公开(公告)日：2010-06-22
申请号：US09259620
申请日：1999-02-26
申请人： James Q. Mi , Vishesh Parikh , Albert Y. Teng
发明人： James Q. Mi , Vishesh Parikh , Albert Y. Teng
IPC分类号： G06F13/00
CPC分类号： G06F21/73 , G06F21/31
摘要： A computer system includes an interface and a processor. The interface is adapted to receive a request from another computer system for identification of the first computer system. The adapter also furnishes a hash value that identifies the first computer system to the other computer system. The processor is coupled to the interface and is adapted to encrypt an identifier that identifies the first computer system with a key associated with the other computer system to provide the hash value.
摘要翻译：计算机系统包括接口和处理器。该接口适于从另一计算机系统接收用于识别第一计算机系统的请求。适配器还提供将第一计算机系统识别到另一计算机系统的哈希值。处理器耦合到接口，并且适于加密用与另一计算机系统相关联的密钥来标识第一计算机系统的标识符，以提供散列值。

7. 发明授权

US5608679A Fast internal reference cell trimming for flash EEPROM memory 失效
公开(公告)号：US5608679A
公开(公告)日：1997-03-04
申请号：US594415
申请日：1996-01-31
申请人： James Q. Mi , Johnny Javanifard , Dennis Dilley
发明人： James Q. Mi , Johnny Javanifard , Dennis Dilley
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G11C29/52 , G11C29/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/3454 , G11C29/50 , G11C29/52 , G06F2201/81 , G11C16/04 , G11C2029/5006 , G11C2211/5621 , G11C2211/5634
摘要： A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a value such that the charge furnished by each pulse is approximately equal to an allowable variation of the charge from the final value.

8. 发明授权

US5608669A Fast internal reference cell trimming for flash EEPROM memory 失效
标题翻译：用于快速EEPROM存储器的快速内部参考单元修整
公开(公告)号：US5608669A
公开(公告)日：1997-03-04
申请号：US599123
申请日：1996-02-09
申请人： James Q. Mi , Johnny Javanifard , Dennis Dilley
发明人： James Q. Mi , Johnny Javanifard , Dennis Dilley
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G11C29/52 , G11C7/00 , G11C29/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/3454 , G11C29/50 , G11C29/52 , G06F2201/81 , G11C16/04 , G11C2029/5006 , G11C2211/5621 , G11C2211/5634
摘要： A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a value such that the charge furnished by each pulse is approximately equal to an allowable variation of the charge from the final value.
摘要翻译：一种用于在存储器件上存储电荷的方法，包括以下步骤：向存储器件提供第一充电脉冲，以将器件充电至小于最终电平的第一电平; 测试费用的价值以确定费用是否大于第一级; 如果所述电荷的值小于所述第一电平，则向所述存储器件提供第二组充电脉冲，所述第二组脉冲的每个脉冲的持续时间是所述第一脉冲持续时间的一部分，足以将装置充电到第一级的值; 测试电荷的值以确定在第二组脉冲的每个脉冲之后电荷是否大于第一电平; 并且一旦所述电荷已经测试大于所述第一电平，则向所述存储器件的端子提供第三组充电脉冲，所述第三组脉冲的每个脉冲的持续时间是所述脉冲持续时间的一部分第二组脉冲和使得由每个脉冲提供的电荷近似等于电荷与最终值的容许变化的值。

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