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1. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

2. 发明申请

US20120185672A1 LOCAL-ONLY SYNCHRONIZING OPERATIONS 审中-公开
标题翻译：本地同步操作
公开(公告)号：US20120185672A1
公开(公告)日：2012-07-19
申请号：US13008498
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/526 , G06F12/0815 , G06F2209/521
摘要： Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The second memory layer is shared via coherency operations among the first core and one or more second cores. The first core may perform one or more synchronization operations on the shared data without requiring interaction from the second memory layer.
摘要翻译：通过核心对由多个核心共享的数据执行一系列连续同步操作可以包括指示即将到来的对共享数据的同步操作的第一核心。第二存储器层存储共享数据并跟踪第一核心对共享数据的所有权。通过第一核心和一个或多个第二核心之间的一致性操作来共享第二存储器层。第一核可以对共享数据执行一个或多个同步操作，而不需要来自第二存储器层的交互。

3. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明申请

US20110246582A1 Message Passing with Queues and Channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US20110246582A1
公开(公告)日：2011-10-06
申请号：US12750363
申请日：2010-03-30
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F15/16
CPC分类号： G06F9/546
摘要： In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.
摘要翻译：在一个实施例中，发送线程接收标识目的地节点的标识符和指向数据的指针。响应于接收到标识符和数据指针，发送线程创建第一个发送请求。发送线程从多个信道中选择所选择的信道。所选择的信道包括所选择的切换队列和所选择的消息单元的标识。每个通道标识不同的消息单元。所选择的切换队列是随机访问的。如果所选择的切换队列包含可用条目，则发送线程将第一个发送请求添加到所选择的切换队列。如果所选择的切换队列不包含可用条目，则发送线程从所选择的切换队列中移除第二发送请求，并将第二发送请求发送到所选择的消息单元。

5. 发明授权

US08543722B2 Message passing with queues and channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US08543722B2
公开(公告)日：2013-09-24
申请号：US12750363
申请日：2010-03-30
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F15/16
CPC分类号： G06F9/546
摘要： In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.
摘要翻译：在一个实施例中，发送线程接收标识目的地节点的标识符和指向数据的指针。响应于接收到标识符和数据指针，发送线程创建第一个发送请求。发送线程从多个信道中选择所选择的信道。所选择的信道包括所选择的切换队列和所选择的消息单元的标识。每个通道标识不同的消息单元。所选择的切换队列是随机访问的。如果所选择的切换队列包含可用条目，则发送线程将第一个发送请求添加到所选择的切换队列。如果所选择的切换队列不包含可用条目，则发送线程从所选择的切换队列中移除第二发送请求，并将第二发送请求发送到所选择的消息单元。

6. 发明授权

US08621167B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08621167B2
公开(公告)日：2013-12-31
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

7. 发明申请

US20110173403A1 USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US20110173403A1
公开(公告)日：2011-07-14
申请号：US12684367
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F13/28 , G06F3/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

8. 发明申请

US20120198118A1 USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US20120198118A1
公开(公告)日：2012-08-02
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

9. 发明授权

US08275964B2 Hardware support for collecting performance counters directly to memory 失效
标题翻译：硬件支持将性能计数器直接收集到内存中
公开(公告)号：US08275964B2
公开(公告)日：2012-09-25
申请号：US12684172
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.
摘要翻译：在一个方面，在性能计数器直接收集到存储器的硬件支持可以包括多个性能计数器，可操作以收集一个或多个所选活动的一个或多个计数。第一存储元件可以用于存储存储器位置的地址。第二存储元件可以用于存储指示硬件是否应该开始复制的值。状态机可操作用于检测第二存储元件中的值，并且触发多个性能计数器中所选择的一个或多个性能计数器中的数据的硬件复制到其地址存储在第一存储元件中的存储单元。

10. 发明授权

US08275954B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08275954B2
公开(公告)日：2012-09-25
申请号：US12684367
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

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