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1. 发明授权

US06667955B1 Switching fabric system having at least one subsystem including switch core elements arranged in port expansion architecture 失效
标题翻译：具有至少一个子系统的交换结构系统包括以端口扩展架构布置的交换机核心元件
公开(公告)号：US06667955B1
公开(公告)日：2003-12-23
申请号：US09315907
申请日：1999-05-20
申请人： Alain Blanc , Sylvie Gohl , Alain Pinzaglia , Menahem Kaplan
发明人： Alain Blanc , Sylvie Gohl , Alain Pinzaglia , Menahem Kaplan
IPC分类号： H04J116
CPC分类号： H04Q3/52 , H04L12/5601 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/455 , H04L2012/5609 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13167 , H04Q2213/13353
摘要： A Switch Fabric system comprising at least one Switch Fabric subsystem (100, 200) further including a set of Switch cores elements (111, 112, 121, 122) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters (1, 2) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core (111, 211) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.
摘要翻译：一种交换矩阵系统，包括至少一个交换结构子系统（100,200），其还包括一组交换机核心元件（111,112,121,122），其安装在端口扩展中，允许至少连接第一和第二组的协议适配器（1,2）。主交换机控制器（PSC）完全了解交换机的拓扑结构，例如子系统的数量，端口扩展的性质等等，而每个辅助交换机控制器只对该拓扑结构的知识有限。在每个子系统中具有全双工通信能力的特定交换机核心（111,211）被分配为在相同交换结构子系统中的PSC和其他SSC之间的通信的关键功能。

2. 发明授权

US06683854B1 System for checking data integrity in a high speed packet switching network node 失效
标题翻译：用于检查高速分组交换网络节点中的数据完整性的系统
公开(公告)号：US06683854B1
公开(公告)日：2004-01-27
申请号：US09271953
申请日：1999-03-18
申请人： Alain Blanc , Patrick Jeanniot , Alain Pinzaglia
发明人： Alain Blanc , Patrick Jeanniot , Alain Pinzaglia
IPC分类号： H04L100
CPC分类号： H04L1/24
摘要： A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.
摘要翻译：一种用于检查高速分组交换网络节点中的交换单元中的数据传输的完整性的系统，其中通过将数据从第一移位寄存器同时移位到目标设备移位寄存器来执行多播。器件寄存器的输出反馈到第一移位寄存器。检查系统包括用于通过一组选择线选择目标的装置选择电路和一个负或门电路。选择线信号和第一寄存器输出是或门的输入，其输出被反馈到第一寄存器。比较器电路具有由器件选择线和器件寄存器的输出提供的输入。处理器将第一寄存器的内容与逻辑比较器电路的输出进行比较，以测试数据是否已正确组播到目标。

3. 发明授权

US06597656B1 Switch system comprising two switch fabrics 失效
标题翻译：交换机系统包括两个交换结构
公开(公告)号：US06597656B1
公开(公告)日：2003-07-22
申请号：US09317006
申请日：1999-05-24
申请人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
发明人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
IPC分类号： H04L122
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/309 , H04L49/455 , H04L2012/5627 , H04L2012/5647
摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.
摘要翻译：一种具有至少两个交换结构的交换系统。每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。两个交换机核心中的掩码寄存器加载互补值。

4. 发明授权

US5359709A Apparatus and method for providing multiple operating configurations in data circuit terminating equipment 失效
标题翻译：在数据电路终端设备中提供多种操作配置的装置和方法
公开(公告)号：US5359709A
公开(公告)日：1994-10-25
申请号：US826504
申请日：1992-01-27
申请人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
发明人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
IPC分类号： H04L5/00 , H04L27/00 , H04L29/06 , H04L29/10 , G06F13/42
CPC分类号： H04L29/06 , H04L27/00
摘要： Multiple operating configurations in data circuit terminating equipment (DCE) are enabled through multiple queues stored in a random access memory and which are loaded with bits and characters coming either from data terminating equipment (DTE) or the telecommunications line. The DSP processor stores bits provided by a transmit circuit in a first queue, determines characters from the bits stored in the first queue based on a first transmission protocol and stores the characters in a second queue. A third queue is used by a control processor to store characters to be transmitted to a remote DCE. The DSP processor determines bits to be transmitted from the characters stored in a third queue based on a second transmission protocol, and stores those bits in a fourth queue. When the DCE is operating in a synchronous mode, the DSP processor determines PCM words for transmission based on the contents of the second queue and stores them in a fifth queue for transmission. Similarly, when the DCE switches to an asynchronous mode, the DSP processor determines PCM words based on the contents of the fourth queue and stores them in the fifth queue for transmission. A similar queue arrangement is provided for the receive circuitry of the DCE.
摘要翻译：数据电路终端设备（DCE）中的多种操作配置通过存储在随机存取存储器中的多个队列启用，并且装载有来自数据终端设备（DTE）或电信线路的位和字符。 DSP处理器将由发送电路提供的位在第一队列中存储，基于第一传输协议从存储在第一队列中的比特确定字符，并将该字符存储在第二队列中。控制处理器使用第三个队列来存储要发送到远程DCE的字符。 DSP处理器基于第二传输协议确定从存储在第三队列中的字符发送的比特，并将这些比特存储在第四队列中。当DCE工作在同步模式时，DSP处理器根据第二个队列的内容来确定用于传输的PCM字，并将其存储在第五个队列中进行传输。类似地，当DCE切换到异步模式时，DSP处理器基于第四队列的内容来确定PCM字，并将它们存储在第五队列中以进行传输。为DCE的接收电路提供了类似的队列布置。

5. 发明授权

US06661786B1 Service message system for a switching architecture 失效
公开(公告)号：US06661786B1
公开(公告)日：2003-12-09
申请号：US09315446
申请日：1999-05-20
申请人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
发明人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
IPC分类号： H04L1250
CPC分类号： H04L49/1523 , H04L49/552
摘要： A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.

6. 发明授权

US6125114A Switching system comprising distributed elements allowing attachment to line adapters, and having multicasting capabilities 失效
标题翻译：交换系统包括允许附加到线路适配器并具有多播功能的分布式元件
公开(公告)号：US6125114A
公开(公告)日：2000-09-26
申请号：US992015
申请日：1997-12-17
申请人： Alain Blanc , Laurent Nicolas , Sylvie Gohl
发明人： Alain Blanc , Laurent Nicolas , Sylvie Gohl
IPC分类号： H04L12/54 , H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/203 , H04L49/255 , H04L49/309 , H04Q11/0478 , H04L2012/5627 , H04L2012/5672
摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.
摘要翻译：一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。每个电路的接收部分包括用于向每个单元引入至少一个额外字节的装置。额外的字节被保留用于携带用于在第一步骤中控制交换结构的路由报头，然后由PINT电路用于第二步中由发送部分接收信元。每个PINT电路的发送部分包括控制模块，其接收在相应输出端口处生成的所有单元，并根据额外字节的值来控制是否丢弃该单元。

7. 发明授权

US06411599B1 Fault tolerant switching architecture 失效
标题翻译：容错交换架构
公开(公告)号：US06411599B1
公开(公告)日：2002-06-25
申请号：US09204394
申请日：1998-12-02
申请人： Alain Blanc , Sylvie Gohl , Michel Poret
发明人： Alain Blanc , Sylvie Gohl , Michel Poret
IPC分类号： H04L122
CPC分类号： H04L49/557 , H04L1/22 , H04L12/5601 , H04L49/103 , H04L49/30 , H04L49/45 , H04L2012/5627
摘要： A fault tolerant switching architecture is provided with two separate switch fabrics each having a switch cure located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element has both a SCAL receive element and a SCAL transmit element for access to a corresponding input and output port of the swatch core. A set of port adapters is distributed at different physical areas, with each connected switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive cells from either one of the switch cores. Each switch fabric can detect an internal breakdown condition occurring in one of its element and send an error control signal to the peer element located in the other switch fabric. Each switch core extracts the Switch Routing Header (SRH) from the cells entering the switch core, and a routing table for obtaining a bit map value that indicates the output ports to which the cell should be routed. An additional controllable masking mechanism is used for altering the value of the bit map in response to the detection of the error control signal from the peer switch core. The routing process is then performed with the altered value of the bitmap.
摘要翻译：具有两个单独的交换结构的容错交换体系结构，每个开关结构具有位于集中式建筑物中的开关固化和分布在不同物理区域中的一组SCAL元件。每个SCAL元件都具有SCAL接收元件和SCAL传输元件，用于访问样本核心的相应输入和输出端口。一组端口适配器分布在不同的物理区域，每个连接的交换结构经由特定的SCAL元件，使得每个交换机核心接收来自任何端口适配器的单元序列，并且相反，任何端口适配器可以接收来自开关核心。每个交换结构可以检测在其元件之一中发生的内部故障状况，并向位于另一个交换结构中的对等元件发送错误控制信号。每个交换机核心从进入交换机核心的小区提取交换路由报头（SRH），以及路由表，用于获取指示该小区应路由的输出端口的位图值。响应于来自对等交换机核心的错误控制信号的检测，使用附加的可控掩蔽机制来改变位图的值。然后使用位图的改变值执行路由过程。

8. 发明授权

US08085789B2 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US08085789B2
公开(公告)日：2011-12-27
申请号：US12365091
申请日：2009-02-03
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.
摘要翻译：公开了一种使用请求/确认机制来选择在折叠的虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。基于选择机制的自由度选择入口端口的出口位置。可以通过确定进入端口可以发送分组的出口位置的数量并确定出口位置可以从哪个入口端口接收分组的数目的入口端口，从折叠的虚拟输出排队阵列导出自由度。分析所有排队的分组以分配到出口位置，以较小的自由度开始，并以更大的自由度结束，从而提供有效的切换分配和确认。

9. 发明授权

US07430167B2 Method and system to enable an adaptive load balancing in a parallel packet switch 失效
标题翻译：在并行分组交换机中实现自适应负载均衡的方法和系统
公开(公告)号：US07430167B2
公开(公告)日：2008-09-30
申请号：US10711320
申请日：2004-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： G06F11/00
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/25 , H04L49/30 , H04L49/3045
摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.
摘要翻译：基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统，位于平面开关芯内。根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

10. 发明申请

US20060025945A1 Method and systems for optimizing high-speed signal transmission 失效
标题翻译：用于优化高速信号传输的方法和系统
公开(公告)号：US20060025945A1
公开(公告)日：2006-02-02
申请号：US11235856
申请日：2005-09-27
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： G06F19/00
CPC分类号： H04L25/03343 , H04L1/0001 , H04L1/20 , H04L7/0337 , H04L2025/03375
摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.
摘要翻译：公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

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