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1. 发明授权

US08085789B2 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US08085789B2
公开(公告)日：2011-12-27
申请号：US12365091
申请日：2009-02-03
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.
摘要翻译：公开了一种使用请求/确认机制来选择在折叠的虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。基于选择机制的自由度选择入口端口的出口位置。可以通过确定进入端口可以发送分组的出口位置的数量并确定出口位置可以从哪个入口端口接收分组的数目的入口端口，从折叠的虚拟输出排队阵列导出自由度。分析所有排队的分组以分配到出口位置，以较小的自由度开始，并以更大的自由度结束，从而提供有效的切换分配和确认。

2. 发明授权

US07430167B2 Method and system to enable an adaptive load balancing in a parallel packet switch 失效
标题翻译：在并行分组交换机中实现自适应负载均衡的方法和系统
公开(公告)号：US07430167B2
公开(公告)日：2008-09-30
申请号：US10711320
申请日：2004-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： G06F11/00
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/25 , H04L49/30 , H04L49/3045
摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.
摘要翻译：基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统，位于平面开关芯内。根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

3. 发明申请

US20090141733A1 ALGORTIHM AND SYSTEM FOR SELECTING ACKNOWLEDGMENTS FROM AN ARRAY OF COLLAPSED VOQ'S 失效
标题翻译：从收集的VOQ的阵列中选择确认的算法和系统
公开(公告)号：US20090141733A1
公开(公告)日：2009-06-04
申请号：US12365091
申请日：2009-02-03
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/56
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制中尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

4. 发明申请

US20050063301A1 METHOD AND SYSTEM TO ENABLE AN ADAPTIVE LOAD BALANCING IN A PARALLEL PACKET SWITCH 失效
标题翻译：在平行分组开关中启用自适应负载平衡的方法和系统
公开(公告)号：US20050063301A1
公开(公告)日：2005-03-24
申请号：US10711320
申请日：2004-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： H04J3/14 , H04L12/54 , H04L12/56
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/25 , H04L49/30 , H04L49/3045
摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.
摘要翻译：基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统，位于平面开关芯内。根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

5. 发明申请

US20050053077A1 System and method for collapsing VOQ'S of a packet switch fabric 有权
标题翻译：用于折叠分组交换结构的VOQ的系统和方法
公开(公告)号：US20050053077A1
公开(公告)日：2005-03-10
申请号：US10894582
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30 , H04L49/103 , H04L49/3027 , H04L49/3045
摘要： A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.
摘要翻译：公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

6. 发明授权

US07486683B2 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US07486683B2
公开(公告)日：2009-02-03
申请号：US10894681
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制内尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

7. 发明申请

US20050053078A1 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US20050053078A1
公开(公告)日：2005-03-10
申请号：US10894681
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制中尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

8. 发明授权

US07769003B2 Data packet switch and method of operating same 失效
标题翻译：数据包交换机和操作方法相同
公开(公告)号：US07769003B2
公开(公告)日：2010-08-03
申请号：US11852661
申请日：2007-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： H04L12/50 , H04Q11/00 , H04L12/28 , H04L12/56
CPC分类号： H04L49/15 , H04L49/103 , H04L49/1523 , H04L49/201 , H04L49/253 , H04L49/90
摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
摘要翻译：包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间被披露。当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播交通。给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

9. 发明授权

US07706394B2 System and method for collapsing VOQ's of a packet switch fabric 有权
标题翻译：用于折叠分组交换结构的VOQ的系统和方法
公开(公告)号：US07706394B2
公开(公告)日：2010-04-27
申请号：US10894582
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30 , H04L49/103 , H04L49/3027 , H04L49/3045
摘要： A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.
摘要翻译：公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

10. 发明授权

US07289523B2 Data packet switch and method of operating same 失效
标题翻译：数据包交换机和操作方法相同
公开(公告)号：US07289523B2
公开(公告)日：2007-10-30
申请号：US10243294
申请日：2002-09-12
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28 , H04J3/06
CPC分类号： H04L49/15 , H04L49/103 , H04L49/1523 , H04L49/201 , H04L49/253 , H04L49/90
摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
摘要翻译：包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间被披露。当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播交通。给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

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