专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090002084A1 Oscillator 审中-公开
标题翻译：振荡器
公开(公告)号：US20090002084A1
公开(公告)日：2009-01-01
申请号：US11658615
申请日：2005-07-13
申请人： Akira Inoue , Kouji Katayama , Takeshi Takagi
发明人： Akira Inoue , Kouji Katayama , Takeshi Takagi
IPC分类号： H03B5/12
CPC分类号： H01L27/088 , H01L27/0617 , H01L27/092 , H03B5/1203 , H03B5/1215 , H03B5/1228 , H03K3/0315 , H03K3/0322 , H03K3/354
摘要： In an oscillator of the present invention, each of field-effect transistors (12) and (13) contained as amplifier elements is a buried-channel transistor including: a body region formed on a semiconductor substrate, a source region and a drain region formed on the body region and having a different conductivity type from that of the body region, a buried channel layer formed between the source region and the drain region, and a gate electrode formed above the buried channel layer with a gate insulating film interposed therebetween, wherein body terminals (b12) and (b13) electrically connected to the body region are connected to a power supply wire to which a power supply potential (Vdd) is applied.
摘要翻译：在本发明的振荡器中，包含作为放大器元件的场效应晶体管（12）和（13）中的每一个是埋入沟道晶体管，其包括：形成在半导体衬底上的体区，形成源区和漏区在体区域具有与体区不同的导电类型，形成在源极区域和漏极区域之间的掩埋沟道层，以及在掩埋沟道层上方形成有栅极绝缘膜的栅电极，其中，电连接到主体区域的主体端子（b12）和（b13）连接到施加电源电位（Vdd）的电源线。

2. 发明授权

US07205586B2 Semiconductor device having SiGe channel region 有权
标题翻译：具有SiGe沟道区的半导体器件
公开(公告)号：US07205586B2
公开(公告)日：2007-04-17
申请号：US10851073
申请日：2004-05-24
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L31/072
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203 , H01L29/161 , H01L29/165 , H01L29/7782 , H01L29/783 , H01L29/78615 , H01L29/78648 , H01L29/78687
摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.
摘要翻译： HDTMOS包括Si衬底，掩埋氧化物膜和半导体层。半导体层包括上硅膜，外延生长的Si缓冲层，外延生长的SiGe膜和外延生长的Si膜。此外，HDTMOS包括n型高浓度Si体区域，n + Si区域，含有n型低浓度杂质的SiGe沟道区域，n型低浓度Si覆盖层，以及作为用于电连接栅电极和Si体区的导体构件的接触。本发明通过在沟道层使用载流子行进的带边缘处的电位较小的材料，而不是构成体区的材料的情况下，使阈值电压保持较小。

3. 发明授权

US06781163B2 Heterojunction field effect transistor 有权
标题翻译：异质结场效应晶体管
公开(公告)号：US06781163B2
公开(公告)日：2004-08-24
申请号：US10311293
申请日：2002-12-17
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L310328
CPC分类号： H01L29/802 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/78687
摘要： A region of an Si layer (15) located between source and drain regions (19 and 20) is an Si body region (21) which contains an n-type impurity of high concentration. An Si layer (16) and an SiGe layer (17) are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer (17) located between the source and drain regions (19 and 20) are an Si buffer region (22) and an SiGe channel region (23), respectively, which contain the n-type impurity of low concentration. A region of an Si film (18) located directly under a gate insulating film (12) is an Si cap region (24) into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.
摘要翻译：位于源极和漏极区域（19和20）之间的Si层（15）的区域是包含高浓度的n型杂质的Si体区域（21）。处于生长状态的Si层（16）和SiGe层（17）是未掺杂n型杂质的未掺杂层。位于源极和漏极区域（19和20）之间的Si层16和SiGe层（17）的区域分别是包含n型的Si缓冲区（22）和SiGe沟道区（23）低浓度的杂质。位于栅极绝缘膜（12）正下方的Si膜（18）的区域是掺杂有p型杂质（5×10 17原子·cm -3）的Si帽区域（24）。因此，可以实现抑制阈值电压增加的半导体装置。

4. 发明授权

US07564073B2 CMOS and HCMOS semiconductor integrated circuit 失效
标题翻译： CMOS和HCMOS半导体集成电路
公开(公告)号：US07564073B2
公开(公告)日：2009-07-21
申请号：US11294566
申请日：2005-12-06
申请人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
发明人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
IPC分类号： H01L27/04
CPC分类号： H01L21/823807
摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.
摘要翻译：根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管形成区域和一对第二装置形成区域。

5. 发明授权

US07084026B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07084026B2
公开(公告)日：2006-08-01
申请号：US10913383
申请日：2004-08-09
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/802 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/78687
摘要： A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.
摘要翻译：位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。位于栅极绝缘膜12正下方的Si膜18的区域是Si帽区域24，其中p型杂质（5×10 17原子％-3重量％）掺杂。因此，可以实现抑制阈值电压增加的半导体装置。

6. 发明申请

US20060054944A1 Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054944A1
公开(公告)日：2006-03-16
申请号：US11260197
申请日：2005-10-28
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

7. 发明申请

US20050093020A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050093020A1
公开(公告)日：2005-05-05
申请号：US10983610
申请日：2004-11-09
申请人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
发明人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/77 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L21/84 , H01L27/092 , H01L27/115 , H01L27/12 , H01L29/10 , H01L29/78 , H01L29/786 , H01L29/80 , H01L31/0392
CPC分类号： H01L29/802 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/10873 , H01L27/11502 , H01L27/11507 , H01L27/1203 , H01L27/1214 , H01L27/1222 , H01L28/55 , H01L29/1054 , H01L29/783 , H01L29/78687
摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
摘要翻译：依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。用EHF波照射局部加热电介质膜，例如PZT膜。结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

8. 发明授权

US07235830B2 Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07235830B2
公开(公告)日：2007-06-26
申请号：US11260197
申请日：2005-10-28
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

9. 发明授权

US07170110B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07170110B2
公开(公告)日：2007-01-30
申请号：US10983610
申请日：2004-11-09
申请人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
发明人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
IPC分类号： H01L29/161 , H01L29/772
CPC分类号： H01L29/802 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/10873 , H01L27/11502 , H01L27/11507 , H01L27/1203 , H01L27/1214 , H01L27/1222 , H01L28/55 , H01L29/1054 , H01L29/783 , H01L29/78687
摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
摘要翻译：依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。用EHF波照射局部加热电介质膜，例如PZT膜。结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

10. 发明申请

US20050133834A1 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050133834A1
公开(公告)日：2005-06-23
申请号：US10948747
申请日：2004-09-24
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66636 , H01L21/28202 , H01L29/1054 , H01L29/518 , H01L29/665 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.
摘要翻译：本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于通道层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式