专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100047997A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20100047997A1
公开(公告)日：2010-02-25
申请号：US12505020
申请日：2009-07-17
申请人： Akihiro ISHIZUKA , Shinya SASAGAWA , Motomu KURATA , Atsushi HIKOSAKA , Taiga MURAOKA , Hitoshi NAKAYAMA
发明人： Akihiro ISHIZUKA , Shinya SASAGAWA , Motomu KURATA , Atsushi HIKOSAKA , Taiga MURAOKA , Hitoshi NAKAYAMA
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.
摘要翻译：本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿脆化区域分离，由此在基底基板上形成半导体层氧化膜。

2. 发明申请

US20120288993A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120288993A1
公开(公告)日：2012-11-15
申请号：US13466664
申请日：2012-05-08
申请人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Hiroshi FUJIKI
发明人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Hiroshi FUJIKI
IPC分类号： H01L21/34
CPC分类号： H01L29/66969 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L29/7869 , H01L29/78696
摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.
摘要翻译：为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层，除了含有氯的气体之外，还使用含有氧或氟的气体。

3. 发明申请

US20110207269A1 TRANSISTOR AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20110207269A1
公开(公告)日：2011-08-25
申请号：US13026520
申请日：2011-02-14
申请人： Shinya SASAGAWA , Masashi TSUBUKU , Hitoshi NAKAYAMA , Daigo SHIMADA
发明人： Shinya SASAGAWA , Masashi TSUBUKU , Hitoshi NAKAYAMA , Daigo SHIMADA
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/32136 , H01L21/32139 , H01L29/66969 , H01L29/7869
摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
摘要翻译：晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

4. 发明申请

US20120012836A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120012836A1
公开(公告)日：2012-01-19
申请号：US13174960
申请日：2011-07-01
申请人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Masashi TSUBUKU , Daigo SHIMADA
发明人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Masashi TSUBUKU , Daigo SHIMADA
IPC分类号： H01L29/786 , H01L21/44 , H01L21/336
CPC分类号： H01L29/66969 , H01L22/14 , H01L27/088 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/7869
摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
摘要翻译：当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于采用第一蚀刻工艺。当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

5. 发明申请

US20120003797A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120003797A1
公开(公告)日：2012-01-05
申请号：US13159804
申请日：2011-06-14
申请人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Masashi TSUBUKU , Daigo SHIMADA
发明人： Shinya SASAGAWA , Hitoshi NAKAYAMA , Masashi TSUBUKU , Daigo SHIMADA
IPC分类号： H01L21/336
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/66969
摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.
摘要翻译：当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于采用第一蚀刻工艺。在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。

6. 发明申请

US20080179298A1 METHOD OF DETECTING AN OBJECT TO BE DETECTED IN A JOINING DEVICE, JOINING DEVICE, AND JOINING METHOD 审中-公开
标题翻译：检测在接合装置中检测的对象的方法，接合装置和接合方法
公开(公告)号：US20080179298A1
公开(公告)日：2008-07-31
申请号：US12020682
申请日：2008-01-28
申请人： Hitoshi NAKAYAMA , Naoki Takeshima
发明人： Hitoshi NAKAYAMA , Naoki Takeshima
IPC分类号： B23K3/06 , B23K1/005 , G01J5/20 , G01J1/02
CPC分类号： B23K3/0623 , B23K1/0056 , B23K3/04
摘要： Provided is a detection method of detecting presence or absence of an object to be detected in an object hold portion that is used together with an irradiation portion that irradiates the object to be detected with a heat ray, holds the object to be detected, and has an opening, the detection method including: imaging an image signal in a predetermined region having the opening by an imaging device; and making an irradiation optical path of the irradiation portion and an imaging optical path of the imaging device substantially coincide with each other within the opening by an optical unit.
摘要翻译：本发明提供一种检测方法，其检测与被照射被检测体的照射部一起与热射线一起使用的物体保持部中的被检体的存在或不存在，保持被检测体，并具有所述检测方法包括：通过成像装置对具有所述开口的预定区域中的图像信号进行成像; 并且通过光学单元使得照射部分的照射光路和成像装置的成像光路在开口内基本上彼此重合。

7. 发明申请

US20120236155A1 TERAHERTZ WAVE GENERATION DEVICE, LIGHT SOURCE DEVICE, CAMERA, IMAGING DEVICE, AND MEASUREMENT DEVICE 有权
标题翻译： TERAHERTZ波形发生装置，光源装置，相机，成像装置和测量装置
公开(公告)号：US20120236155A1
公开(公告)日：2012-09-20
申请号：US13405434
申请日：2012-02-27
申请人： Hitoshi NAKAYAMA
发明人： Hitoshi NAKAYAMA
IPC分类号： H04N5/33 , G01J5/10 , B01J19/12
CPC分类号： G01N21/3581 , B82Y20/00 , H01S5/0057 , H01S5/026 , H01S5/0265 , H01S5/0609 , H01S5/0625 , H01S5/0657 , H01S5/34313 , H01S5/4031
摘要： A terahertz wave generation device includes a light source device emitting an optical pulse, and an antenna generating a terahertz wave through irradiation of the optical pulse that is emitted from the light source device onto the antenna, wherein the light source device includes an optical pulse generation unit generating the optical pulse, a first pulse compression unit performing pulse compression based on saturable absorbers with respect to the optical pulse generated by the optical pulse generation unit, a second pulse compression unit performing pulse compression based on group velocity dispersion compensation with respect to the optical pulse already compressed by the first pulse compression unit, and an amplifying unit installed between the first pulse compression unit and the second pulse compression unit to amplify the optical pulse emitted from the first pulse compression unit.
摘要翻译：太赫兹波发生装置包括发射光脉冲的光源装置和通过从光源装置照射到天线上而产生太赫兹波的天线，其中光源装置包括光脉冲产生产生光脉冲的单元，相对于由光脉冲发生单元产生的光脉冲，基于可饱和吸收体执行脉冲压缩的第一脉冲压缩单元，基于组速度色散补偿执行脉冲压缩的第二脉冲压缩单元已经被第一脉冲压缩单元压缩的光脉冲以及安装在第一脉冲压缩单元和第二脉冲压缩单元之间的放大单元，用于放大从第一脉冲压缩单元发出的光脉冲。

8. 发明申请

US20090279580A1 SURFACE-EMITTING TYPE SEMICONDUCTOR LASER AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：表面发射型半导体激光器及其制造方法
公开(公告)号：US20090279580A1
公开(公告)日：2009-11-12
申请号：US12502748
申请日：2009-07-14
申请人： Hitoshi NAKAYAMA , Tsugio IDE , Tsuyoshi KANEKO
发明人： Hitoshi NAKAYAMA , Tsugio IDE , Tsuyoshi KANEKO
IPC分类号： H01S5/183
CPC分类号： H01S5/18355 , H01S5/18308 , H01S5/18311 , H01S5/18338 , H01S5/1835 , H01S5/423 , H01S2301/176
摘要： To provide surface-emitting type semiconductor lasers and methods of manufacturing the same in which the polarization direction of laser light can be readily controlled, a surface-emitting type semiconductor laser includes a vertical resonator above a substrate. The vertical resonator includes a first mirror, an active layer and a second mirror disposed in this order from the substrate. The vertical resonator has a plurality of unit resonators. An emission region of each of the unit resonators has a diameter that oscillates in a single-mode.
摘要翻译：为了提供表面发射型半导体激光器及其制造方法，其中可以容易地控制激光的偏振方向，表面发射型半导体激光器包括在衬底上方的垂直谐振器。垂直谐振器包括从衬底依次设置的第一反射镜，有源层和第二反射镜。垂直谐振器具有多个单元谐振器。每个单位谐振器的发射区域具有以单模振荡的直径。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式