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1. 发明授权

US5422723A Diffraction gratings for submicron linewidth measurement 失效
$Diffraction gratings for submicron linewidth measurement$
标题翻译：用于亚微米线宽测量的衍射光栅
公开(公告)号：US5422723A
公开(公告)日：1995-06-06
申请号：US948194
申请日：1992-09-21
申请人： Ajit P. Paranjpe , Phillip Chapados, Jr. , Jimmy W. Hosch
发明人： Ajit P. Paranjpe , Phillip Chapados, Jr. , Jimmy W. Hosch
IPC分类号： G01B11/02 , G02B5/18 , H01L21/302 , H01L21/306 , H01L21/3065 , G01B9/02
CPC分类号： G01B11/02
摘要： A test structure and a method of using it for measuring submicron linewidths. Diffraction gratings are made with lines having an unknown linewidth. The grating has a pitch comprises of multiple lines and multiple spaces. This permits a wider "effective pitch" resulting in an increased number of observable diffraction orders. Each order provides an intensity measurement, which can be substituted into a diffraction intensity equation in which intensity is a function of linewidth and other unknown variables. At least as many intensity measurements are obtained as are unknown variables so that a system of equations can be solved for the linewidth. In practice, if the grating lines are made in the same manner as other lines of a product, the width of the latter can be inferred.
摘要翻译：测试结构及其用于测量亚微米线宽的方法。衍射光栅由具有未知线宽的线制成。光栅具有包括多条线和多个空间的间距。这允许更宽的“有效间距”导致可观察的衍射级数的增加。每个顺序都提供强度测量，可以用衍射强度方程来代替强度是线宽和其他未知变量的函数。至少获得与未知变量一样多的强度测量，以便可以求解线宽系数。实际上，如果光栅线以与产品的其它线相同的方式制造，则可以推断后者的宽度。

2. 发明授权

US5361137A Process control for submicron linewidth measurement 失效
标题翻译：亚微米线宽测量的过程控制
公开(公告)号：US5361137A
公开(公告)日：1994-11-01
申请号：US938078
申请日：1992-08-31
申请人： Thomas J. Aton , Phillip Chapados, Jr. , Jimmy W. Hosch , Ajit P. Paranjpe
发明人： Thomas J. Aton , Phillip Chapados, Jr. , Jimmy W. Hosch , Ajit P. Paranjpe
IPC分类号： G01B11/02 , G01B9/02
CPC分类号： G01B11/02
摘要： A method and apparatus for measuring submicron linewidths, using diffraction gratings. A set of "fixed-linewidth variable-pitchwidth" test gratings has a number of gratings, each grating having the same linewidth but having different pitchwidths. These gratings are illuminated to form diffraction patterns. A set of peak intensities of the first or second order diffraction image from each grating is recorded. Either of these intensity values forms a curve around an extrema, which represents the intensity from a grating whose pitchwidth is equal to one-half the linewidth.
摘要翻译：使用衍射光栅测量亚微米线宽的方法和装置。一组“固定线宽可变 - 宽度”测试光栅具有多个光栅，每个光栅具有相同的线宽但具有不同的节距。这些光栅被照亮以形成衍射图案。记录来自每个光栅的一阶或二阶衍射图像的一组峰值强度。这些强度值中的任一个形成围绕极值的曲线，其表示其间距宽度等于线宽的一半的光栅的强度。

3. 发明授权

US06645847B2 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06645847B2
公开(公告)日：2003-11-11
申请号：US10060548
申请日：2002-01-30
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

4. 发明授权

US06596133B1 Method and system for physically-assisted chemical-vapor deposition 失效
标题翻译：物理辅助化学气相沉积的方法和系统
公开(公告)号：US06596133B1
公开(公告)日：2003-07-22
申请号：US09678467
申请日：2001-06-14
申请人： Mehrdad M. Moslehi , Ajit P. Paranjpe
发明人： Mehrdad M. Moslehi , Ajit P. Paranjpe
IPC分类号： C23C1432
CPC分类号： C23C14/3442 , C23C14/0031 , C23C14/3464 , C23C14/56 , C23C16/0281 , C23C16/48 , C23C16/54 , H01J37/3233 , H01J37/34
摘要： An apparatus and method for the deposition of thin film material layers provides improved use of processing chamber space for enhanced processing capability in the fabrication of microelectronic devices. In one embodiment, a physical-vapor deposition target offset from the processing chamber central axis, such as a target having an annular shape and central opening, deposits a material on a substrate while leaving the central region of the processing chamber available for other deposition techniques, including a centrally located sputtering target, CVD showerhead, or ion source. Alternatively, a collimator divides a processing chamber into sub-chambers and allows energetic species from a PVD target or ion source to pass to a substrate located in a separate sub-chamber for interaction with a CVD precursor without mixing the precursor and the plasma associated with the PVD or ion processes. The apparatus supports deposition of material from a single precursor in a manner that mimics atomic layer deposition since the process of subjecting a precursor to energetic species, such as ions or material atoms, allows disassociation of material from the precursor at lower temperatures.
摘要翻译：用于沉积薄膜材料层的装置和方法提供了改进的处理室空间的使用，用于在微电子器件的制造中增强处理能力。在一个实施例中，从处理室中心轴偏移的物理气相沉积靶，例如具有环形形状和中心开口的靶，将材料沉积在衬底上，同时使处理室的中心区域可用于其它沉积技术，包括中心位置的溅射靶，CVD喷头或离子源。或者，准直器将处理室划分为子室，并且允许来自PVD靶或离子源的能量物质传递到位于单独子室中的衬底，用于与CVD前体相互作用，而不混合前体和与 PVD或离子工艺。该设备支持以模拟原子层沉积的方式从单一前体沉积材料，因为使前体经受高能物质如离子或材料原子的过程允许材料在较低温度下与前体分离。

5. 发明授权

US5435379A Method and apparatus for low-temperature semiconductor processing 失效
标题翻译：低温半导体加工方法和装置
公开(公告)号：US5435379A
公开(公告)日：1995-07-25
申请号：US930074
申请日：1992-08-14
申请人： Mehrdad M. Moslehi , Habib N. Najm , Ajit P. Paranjpe , Cecil J. Davis
发明人： Mehrdad M. Moslehi , Habib N. Najm , Ajit P. Paranjpe , Cecil J. Davis
IPC分类号： H01L21/302 , F04B23/02 , F04B49/24 , H01J37/34 , H01L21/00 , H01L21/3065 , H01L21/683 , F28D15/00
CPC分类号： H01L21/67103 , F04B23/028 , F04B49/24 , H01J37/34 , H01J2237/2001 , H01J2237/32
摘要： A chilling system (12) has a container (20) filled with a coolant (22). A pipe (16) traverses within the container (20) and the coolant (22) to a housing (18). Fluid flows within the pipe (16) and becomes chilled through the pipe (16) upon entering the container (20) and the coolant (22). The chilled fluid enters the housing (18) chilling the housing (18) through the pipe (16). In turn, semiconductor substrate (19) in contact with the housing (18) also is chilled.
摘要翻译：冷却系统（12）具有填充有冷却剂（22）的容器（20）。管道（16）在容器（20）和冷却剂（22）内移动到壳体（18）。流体在管道（16）内流动，并且在进入容器（20）和冷却剂（22）时通过管道（16）变冷。冷冻流体通过管道（16）进入冷却壳体（18）的壳体（18）。反过来，与壳体（18）接触的半导体衬底（19）也被冷却。

6. 发明授权

US5434107A Method for planarization 失效
标题翻译：平面化方法
公开(公告)号：US5434107A
公开(公告)日：1995-07-18
申请号：US188498
申请日：1994-01-28
申请人： Ajit P. Paranjpe
发明人： Ajit P. Paranjpe
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/463
CPC分类号： B29C43/003 , H01L21/31051 , B29C2043/025
摘要： A method for planarization of the upper surface of a semiconductor wafer. A wafer with features formed thereon is loaded into the apparatus after having been coated with an interlevel dielectric. Thereafter, the wafer is subjected to suitably elevated temperature while a uniform elevated pressure is applied. Once the temperature and pressure conditions exceed the yield stress of the film, the film will flow and fill the microscopic as well as global depressions in the wafer surface. Thereafter, the temperature and pressure is reduced so that the film will become firm again thereby leaving a planar upper surface on the wafer.
摘要翻译：一种半导体晶片的上表面的平坦化方法。具有形成在其上的特征的晶片在已经涂覆有层间电介质之后被装载到设备中。此后，在施加均匀的升高的压力的同时使晶片经受适当的升高的温度。一旦温度和压力条件超过膜的屈服应力，膜将流动并填充晶片表面的微观以及全局凹陷。此后，降低温度和压力，使得膜再次变得牢固，从而在晶片上留下平坦的上表面。

7. 发明授权

US5249865A Interferometric temperature measurement system and method 失效
标题翻译：干涉测温系统及方法
公开(公告)号：US5249865A
公开(公告)日：1993-10-05
申请号：US874658
申请日：1992-04-27
申请人： Ajit P. Paranjpe , Steven A. Henck , Walter M. Duncan
发明人： Ajit P. Paranjpe , Steven A. Henck , Walter M. Duncan
IPC分类号： G01K11/00 , G01J5/58
CPC分类号： G01J5/58 , G01J5/0003 , G01J5/0007 , G01K11/00
摘要： An interferonmetric temperature measurement system is described for determining the temperature of a sample. The system comprises three detectors for measuring various intensities of a beam of electromagnetic radiation reflected off the sample and circuitry for determining the temperature from the intensities. The detectors measure the intensity of the beam and two orthogonally polarized components of the beam.
摘要翻译：描述了用于确定样品的温度的干涉测量温度测量系统。该系统包括三个检测器，用于测量样品反射的电磁辐射束的各种强度和用于根据强度确定温度的电路。检测器测量光束的强度和光束的两个正交极化分量。

8. 发明授权

US07037574B2 Atomic layer deposition for fabricating thin films 失效
标题翻译：用于制造薄膜的原子层沉积
公开(公告)号：US07037574B2
公开(公告)日：2006-05-02
申请号：US09864714
申请日：2001-05-23
申请人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
发明人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
IPC分类号： H01L21/8242 , H01L21/336 , C30B23/00 , C30B25/00
CPC分类号： H01L21/0228 , B82Y10/00 , B82Y25/00 , B82Y40/00 , C23C16/403 , C23C16/45527 , C23C16/56 , G11B5/3109 , G11B5/3163 , G11B5/3909 , G11B5/3967 , G11B2005/3996 , H01F41/307 , H01L21/02178 , H01L21/02205 , H01L21/0234 , H01L21/3162 , Y10T428/24843
摘要： An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities
摘要翻译：原子层沉积（ALD）工艺通过等离子体退火在不同的膜厚度上沉积微电子结构的薄膜，例如先进的间隙和隧道结应用，以获得所需的本征膜应力和击穿膜强度。 ALD工艺的主要优点是接近100％的阶梯覆盖，其侧壁均匀分布。该方法提供了具有改进的击穿强度（9-10MV / cm）的平滑的（R a aα2），纯的（杂质<1 AT。％），ALO x ）具有商业上可行的吞吐量。

9. 发明授权

US5888899A Method for copper doping of aluminum films 失效
标题翻译：铝膜铜掺杂方法
公开(公告)号：US5888899A
公开(公告)日：1999-03-30
申请号：US829885
申请日：1997-04-02
申请人： Ajit P. Paranjpe
发明人： Ajit P. Paranjpe
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/53219 , H01L2924/0002
摘要： An embodiment of the instant invention is a method of forming a conductive structure over a semiconductor wafer, the method comprising the steps of: forming a first aluminum layer (14, 24) of a thickness; forming a conductive layer (18,28) of a material which is not readily etched by aluminum-etching etchants on the first aluminum layer, the conuctive layer having a thickness; forming a second aluminum layer (20, 30) on the conductive layer, the second aluminum layer having a thickness; patterning and etching the second aluminum layer thereby exposing a portion of the conductive layer; etching the exposed portion of the conductive layer thereby exposing a portion of the first aluminum layer; etching the exposed portion of the first aluminum layer; subjecting semiconductor wafer to a thermal step thereby diffusing the material in the conductive layer from the conductive layer into the first and second aluminum layers; and wherein the thickness of the conductive layer is much thinner than the thicknesses of the first and second aluminum layers. A plurality of aluminum/conductive/aluminum layers may be formed prior to patterning and etching. Preferably, the material of the conductive layer is comprised of: copper, scandium, tantalum, or vanadium, and the conductive layer is approximately 10 to 30 .ANG. thick and comprised of copper. More preferably, the copper layer is approximately 20 .ANG. thick. Preferably, the first aluminum layer is approximately 1500 to 3000 .ANG. thick, and the second aluminum layer is approximately 1500 to 3000 .ANG. thick.
摘要翻译：本发明的一个实施例是在半导体晶片上形成导电结构的方法，该方法包括以下步骤：形成厚度的第一铝层（14,24）; 在所述第一铝层上形成不易被铝蚀刻蚀刻剂蚀刻的材料的导电层（18,28），所述导电层具有厚度; 在所述导电层上形成第二铝层（20,30），所述第二铝层具有厚度; 图案化和蚀刻第二铝层，从而暴露导电层的一部分; 蚀刻导电层的暴露部分，从而暴露第一铝层的一部分; 蚀刻第一铝层的暴露部分; 使半导体晶片经受热步骤，从而将导电层中的材料从导电层扩散到第一和第二铝层中; 并且其中所述导电层的厚度比所述第一和第二铝层的厚度薄得多。可以在图案化和蚀刻之前形成多个铝/导电/铝层。优选地，导电层的材料包括：铜，钪，钽或钒，并且导电层厚度约为10至30埃，由铜构成。更优选地，铜层的厚度约为20。优选地，第一铝层的厚度约为1500至3000，第二铝层的厚度约为1500至3000。

10. 发明授权

US5601366A Method for temperature measurement in rapid thermal process systems 失效
标题翻译：快速热处理系统中温度测量方法
公开(公告)号：US5601366A
公开(公告)日：1997-02-11
申请号：US329014
申请日：1994-10-25
申请人： Ajit P. Paranjpe
发明人： Ajit P. Paranjpe
IPC分类号： G01J5/00 , G01J5/10
CPC分类号： G01J5/0003
摘要： A method for obtaining real-time emissivity and temperature values of a semiconductor wafer in a processing system having at least one lamp (preferably a plurality of lamps arranged in a plurality of zones so as to provide multizone temperature and emissivity values for the semiconductor wafer) arranged in at least one zone, the method using a reference wafer having a known reflectivity and the method comprising the steps of: measuring pyrometry signals for the reference wafer (step 202) and generating calibration curves from the measurements; measuring pyrometry signals for the semiconductor wafer; and obtaining the temperature and emissivity values (step 222) from the calibration curves and the measured pyrometry signals (step 220) for the semiconductor wafer.
摘要翻译：一种在具有至少一个灯（优选为多个区域中布置的多个灯以便为半导体晶片提供多区域温度和发射率值）的处理系统中获得半导体晶片的实时发射率和温度值的方法，布置在至少一个区域中，所述方法使用具有已知反射率的参考晶片，并且所述方法包括以下步骤：测量所述参考晶片的高温测量信号（步骤202）并从所述测量产生校准曲线; 测量半导体晶片的高温测量信号; 并从半导体晶片的校准曲线和测量的高温测量信号（步骤220）获得温度和发射率值（步骤222）。

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