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1. 发明授权

US06645847B2 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06645847B2
公开(公告)日：2003-11-11
申请号：US10060548
申请日：2002-01-30
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

2. 发明授权

US06627995B2 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06627995B2
公开(公告)日：2003-09-30
申请号：US10113191
申请日：2002-04-01
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

3. 发明授权

US06365502B1 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06365502B1
公开(公告)日：2002-04-02
申请号：US09518294
申请日：2000-03-03
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

4. 发明授权

US06461675B2 Method for forming a copper film on a substrate 失效
标题翻译：在基板上形成铜膜的方法
公开(公告)号：US06461675B2
公开(公告)日：2002-10-08
申请号：US09113852
申请日：1998-07-10
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
IPC分类号： C23C1606
CPC分类号： H01L21/76858 , C23C16/0209 , C23C16/0245 , C23C16/0281 , C23C16/18 , H01L21/76843 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L2221/1089
摘要： Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput. Alternatively, the adhesion promotion techniques can avoid the formation of an interface by graduated deposition of a first material and copper.
摘要翻译：通过粘合促进技术增强铜膜如铜互连对衬底底层（例如衬底扩散阻挡层）的粘合性。粘合促进技术可以修复铜膜和基材的界面，以增强铜膜的粘附性，从而高收率地形成嵌入的铜金属线和插塞。例如，种子层（包括铜籽晶层，合金种子层或反应物种子层）的热退火可以修复种子层和基底的界面处的污染。或者，粘合促进技术可以避免通过沉积惰性种子层（例如贵金属（例如铂）或钝化金属种子层）或通过在限制界面的污染最小化的预定条件下沉积籽晶层来污染界面，然后在允许生产量最大化的预定条件下沉积大块铜层。或者，粘合促进技术可以避免通过第一材料和铜的分级沉积形成界面。

5. 发明授权

US06444263B1 Method of chemical-vapor deposition of a material 失效
标题翻译：化学气相沉积材料的方法
公开(公告)号：US06444263B1
公开(公告)日：2002-09-03
申请号：US09663209
申请日：2000-09-15
申请人： Ajit P. Paranjpe , Randhir S. Bubber , Sanjay Gopinath , Thomas R. Omstead , Mehrdad M. Moslehi
发明人： Ajit P. Paranjpe , Randhir S. Bubber , Sanjay Gopinath , Thomas R. Omstead , Mehrdad M. Moslehi
IPC分类号： C23C1616
CPC分类号： C23C16/16 , C23C16/0281
摘要： A method for chemical-vapor deposition of a material film adds precursor decomposition by-product to the precursor flow to suppress premature gas-phase precursor decomposition and improve process repeatability and film quality. In one embodiment, CVD cobalt films are deposited with carbonyl precursors with reduced premature gas-phase reaction and particulate generation by the addition of excess carbon monoxide to the process chamber comprising the precursor flow. The addition of carbon monoxide not only suppresses gas-phase reaction but also improves cobalt film purity. The addition of excess carbon monoxide to CVD cobalt precursor flow provides repeatable deposition of glue and nucleation layers to support CVD copper, and is extendable to the deposition of high purity CVD cobalt for other applications and with other precursors, and also extendable for CVD CoSi2 films and other cobalt-containing applications.
摘要翻译：材料膜的化学气相沉积方法将前体分解副产物添加到前体流中以抑制过早气相前体分解，并提高工艺重复性和膜质量。在一个实施方案中，通过在包含前体流的处理室中加入过量的一氧化碳，将CVD钴膜沉积在羰基前体中，同时减少过早的气相反应和颗粒产生。加入一氧化碳不仅抑制了气相反应，而且还提高了钴膜的纯度。过量的一氧化碳添加到CVD钴前体流中提供了可重复沉积的胶和成核层以支持CVD铜，并且可扩展到用于其它应用和其它前体的高纯度CVD钴的沉积，并且还可用于CVD CoSi 2膜和其他含钴应用。

6. 发明授权

US06294836B1 Semiconductor chip interconnect barrier material and fabrication method 失效
标题翻译：半导体芯片互连屏障材料及制造方法
公开(公告)号：US06294836B1
公开(公告)日：2001-09-25
申请号：US09219147
申请日：1998-12-22
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
摘要翻译：微电子半导体互连结构屏障和沉积方法为高性能器件互连提供改进的导电阻挡材料性质。阻挡层包括选自铂，钯，铱，铑和锡的掺杂剂。阻挡层可以包括选自钽，钨钛，铬和钴的难熔金属，并且还可以包括选自碳，氧和氮的第三元素。通过化学气相沉积可以通过化学气相沉积来沉积掺杂剂和其它阻挡材料以实现良好的阶梯覆盖，并且在一个实施例中，具有良好成核表面的相对适形的薄膜用于随后的金属化，例如铜金属化，屏障抑制铜扩散到其它层的器件，包括金属间电介质，预金属电介质和晶体管结构。

7. 发明授权

US06812126B1 Method for fabricating a semiconductor chip interconnect 失效
标题翻译：半导体芯片互连的制造方法
公开(公告)号：US06812126B1
公开(公告)日：2004-11-02
申请号：US09553933
申请日：2000-04-21
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
摘要翻译：微电子半导体互连结构屏障和沉积方法为高性能器件互连提供改进的导电阻挡材料性质。阻挡层包括选自铂，钯，铱，铑和时间的掺杂剂。阻挡层可以包括选自钽，钨钛，铬和钴的难熔金属，并且还可以包含选自碳，氧和氮的第三元素。可以通过化学气相沉积来沉积掺杂剂和其它阻挡材料以实现良好的阶梯覆盖，并且具有良好成核表面的相对适形的薄膜用于随后的金属化，例如铜金属化。在一个实施例中，屏障抑制铜扩散到器件的其它层，包括金属间电介质，预金属电介质和晶体管结构。

8. 发明授权

US06204204B1 Method and apparatus for depositing tantalum-based thin films with organmetallic precursor 失效
标题翻译：用有机金属前体沉积钽基薄膜的方法和设备
公开(公告)号：US06204204B1
公开(公告)日：2001-03-20
申请号：US09282952
申请日：1999-04-01
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L21302
CPC分类号： H01L21/76862 , C23C16/34 , C23C16/448 , H01L21/28556 , H01L21/76843
摘要： A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality. Resistivity of the barrier film is reduced by flowing a reactive gas with the precursor flow, the reactive gas reducing the carbon content of the barrier film, or by co-deposition of a resistivity-lowering metallic dopant with the precursor solution. Alternatively, resistivity is reduced by controlling the nitrogen content of the film by a post-deposition plasma treatment of the barrier with a reducing gas.
摘要翻译：公开了一种方法和装置，用于通过将含钽的有机金属前体如PEMAT或PDEAT溶解在惰性，低粘度，高分子量，低挥发性中来沉积含钽的扩散阻挡层，例如TaN阻挡层溶剂，如辛烷，庚烷，癸烷或甲苯。前体溶剂溶液蒸发并流过基底以沉积屏障。通过将前体与溶剂的比例保持在通常较低的值，例如约10％的前体，前体溶液具有与溶剂基本相似的粘度。溶剂的沸点基本上类似于前体的沸点，例如在一个大气压下的前体沸点的50％以内，以提高阻挡膜质量的重复性。阻挡膜的电阻率通过使与前体流反应的气体流动，反应气体降低阻挡膜的碳含量，或通过与前体溶液共沉积电阻率降低金属掺杂剂来降低。或者，通过用还原气体对阻挡层进行后期等离子体处理来控制膜的氮含量来降低电阻率。

9. 发明授权

US07037574B2 Atomic layer deposition for fabricating thin films 失效
标题翻译：用于制造薄膜的原子层沉积
公开(公告)号：US07037574B2
公开(公告)日：2006-05-02
申请号：US09864714
申请日：2001-05-23
申请人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
发明人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
IPC分类号： H01L21/8242 , H01L21/336 , C30B23/00 , C30B25/00
CPC分类号： H01L21/0228 , B82Y10/00 , B82Y25/00 , B82Y40/00 , C23C16/403 , C23C16/45527 , C23C16/56 , G11B5/3109 , G11B5/3163 , G11B5/3909 , G11B5/3967 , G11B2005/3996 , H01F41/307 , H01L21/02178 , H01L21/02205 , H01L21/0234 , H01L21/3162 , Y10T428/24843
摘要： An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities
摘要翻译：原子层沉积（ALD）工艺通过等离子体退火在不同的膜厚度上沉积微电子结构的薄膜，例如先进的间隙和隧道结应用，以获得所需的本征膜应力和击穿膜强度。 ALD工艺的主要优点是接近100％的阶梯覆盖，其侧壁均匀分布。该方法提供了具有改进的击穿强度（9-10MV / cm）的平滑的（R a aα2），纯的（杂质<1 AT。％），ALO x ）具有商业上可行的吞吐量。

10. 发明授权

US06596133B1 Method and system for physically-assisted chemical-vapor deposition 失效
标题翻译：物理辅助化学气相沉积的方法和系统
公开(公告)号：US06596133B1
公开(公告)日：2003-07-22
申请号：US09678467
申请日：2001-06-14
申请人： Mehrdad M. Moslehi , Ajit P. Paranjpe
发明人： Mehrdad M. Moslehi , Ajit P. Paranjpe
IPC分类号： C23C1432
CPC分类号： C23C14/3442 , C23C14/0031 , C23C14/3464 , C23C14/56 , C23C16/0281 , C23C16/48 , C23C16/54 , H01J37/3233 , H01J37/34
摘要： An apparatus and method for the deposition of thin film material layers provides improved use of processing chamber space for enhanced processing capability in the fabrication of microelectronic devices. In one embodiment, a physical-vapor deposition target offset from the processing chamber central axis, such as a target having an annular shape and central opening, deposits a material on a substrate while leaving the central region of the processing chamber available for other deposition techniques, including a centrally located sputtering target, CVD showerhead, or ion source. Alternatively, a collimator divides a processing chamber into sub-chambers and allows energetic species from a PVD target or ion source to pass to a substrate located in a separate sub-chamber for interaction with a CVD precursor without mixing the precursor and the plasma associated with the PVD or ion processes. The apparatus supports deposition of material from a single precursor in a manner that mimics atomic layer deposition since the process of subjecting a precursor to energetic species, such as ions or material atoms, allows disassociation of material from the precursor at lower temperatures.
摘要翻译：用于沉积薄膜材料层的装置和方法提供了改进的处理室空间的使用，用于在微电子器件的制造中增强处理能力。在一个实施例中，从处理室中心轴偏移的物理气相沉积靶，例如具有环形形状和中心开口的靶，将材料沉积在衬底上，同时使处理室的中心区域可用于其它沉积技术，包括中心位置的溅射靶，CVD喷头或离子源。或者，准直器将处理室划分为子室，并且允许来自PVD靶或离子源的能量物质传递到位于单独子室中的衬底，用于与CVD前体相互作用，而不混合前体和与 PVD或离子工艺。该设备支持以模拟原子层沉积的方式从单一前体沉积材料，因为使前体经受高能物质如离子或材料原子的过程允许材料在较低温度下与前体分离。

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