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1. 发明授权

US06444529B1 Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor 有权
公开(公告)号：US06444529B1
公开(公告)日：2002-09-03
申请号：US09771449
申请日：2001-01-26
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.

2. 发明授权

US06660600B2 Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors 有权
公开(公告)号：US06660600B2
公开(公告)日：2003-12-09
申请号：US10233020
申请日：2002-08-30
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/823425 , H01L29/41775 , H01L29/41783 , H01L29/665
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.

3. 发明授权

US06211026B1 Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成场效应晶体管的升高的源极/漏极区域的方法以及形成场效应晶体管的方法
公开(公告)号：US06211026B1
公开(公告)日：2001-04-03
申请号：US09203541
申请日：1998-12-01
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/823425 , H01L27/10873 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66545 , Y10S438/947
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.
摘要翻译：描述形成集成电路的方法，形成升高的源极/漏极区域的方法以及形成场效应晶体管的方法。在一个实施例中，在半导体衬底上形成晶体管栅极线。包含未掺杂的半导体材料的层横向地形成在晶体管栅极线附近，并与衬底的半导体材料接合并且包括用于该线的晶体管的升高的源极/漏极材料。随后，将升高的源极/漏极材料提供导电性改性杂质。在另一个实施例中，利用共同的步骤来将升高电导率的杂质提供到升高的源极/漏极材料和栅极线的材料中。在另一个实施例中，首先对未掺杂的半导体层进行图案化和蚀刻，以在提供导电性改性杂质之前提供升高的源/漏区。在另一个实施例中，半导体材料首先被图案化，其中导电性改性杂质被提供到半导体材料的选定部分。随后相对于掺杂的半导体材料部分选择性地去除未掺杂的半导体部分。

4. 发明授权

US07863133B2 Oxide epitaxial isolation 有权
标题翻译：氧化物外延隔离
公开(公告)号：US07863133B2
公开(公告)日：2011-01-04
申请号：US12367409
申请日：2009-02-06
申请人： Lyle Jones
发明人： Lyle Jones
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42332 , H01L29/66825
摘要： Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.
摘要翻译：描述了非易失性存储单元结构，其通过包括在水平应变衬底上形成第一氧化物层的方法形成，形成通过第一氧化物层的至少一个第一凹部到应变衬底，以及形成至少一个垂直外延结构在休息。垂直外延结构的晶格与应变衬底的晶格对准。

5. 发明申请

US20060006442A1 Process for making a silicon-on-insulator ledge and structures achieved thereby 审中-公开
公开(公告)号：US20060006442A1
公开(公告)日：2006-01-12
申请号：US11215404
申请日：2005-08-30
申请人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
发明人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
IPC分类号： H01L27/108
CPC分类号： H01L21/26506 , H01L21/76235 , H01L21/76264 , H01L21/76281 , H01L21/76289 , H01L21/764 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/0214 , H01L27/10811 , H01L27/10844 , H01L27/10873 , H01L27/11521 , H01L27/1203 , H01L28/91 , H01L29/7846
摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

6. 发明授权

US06784076B2 Process for making a silicon-on-insulator ledge by implanting ions from silicon source 有权
标题翻译：通过从硅源注入离子来制造绝缘体上硅栅的工艺
公开(公告)号：US06784076B2
公开(公告)日：2004-08-31
申请号：US10118569
申请日：2002-04-08
申请人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
发明人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
IPC分类号： H01L2176
CPC分类号： H01L27/10873 , H01L21/26506 , H01L21/76235 , H01L21/76264 , H01L21/76281 , H01L21/76289 , H01L21/764 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/0214 , H01L27/10811 , H01L27/10844 , H01L27/11521 , H01L27/1203 , H01L28/91 , H01L29/7846
摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.
摘要翻译：公开了一种制造绝缘体上部分硅片的工艺。在衬底中产生深的注入区域。在横向腔蚀刻期间，深注入区域抵抗蚀刻。侧腔蚀刻用于部分隔离深注入区域上方的有效区域。根据实施例，在各种处理阶段形成深注入区域。还公开了通过该过程实现的主动装置。还公开了一种使用有源器件的系统。

7. 发明申请

US20120127793A1 MEMORY ARRAYS 有权
标题翻译：内存阵列
公开(公告)号：US20120127793A1
公开(公告)日：2012-05-24
申请号：US13359947
申请日：2012-01-27
申请人： Roger W. Lindsay , Lyle Jones
发明人： Roger W. Lindsay , Lyle Jones
IPC分类号： G11C16/04
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and where the first row of memory cells is successively adjacent to the second row of memory cells. The memory array also includes alternating first and second bit lines, where each of the memory cells of the first row of memory cells is coupled to a respective one of the first bit lines, where each of the memory cells of the second row of memory cells is coupled to a respective one of the second bit lines, and wherein the first bit lines are different from the second bit lines.
摘要翻译：存储器阵列包括控制栅极，其中耦合到控制栅极的第一侧的每个存储器单元位于第一行存储器单元内，并且耦合到控制栅极的第二侧的每个存储单元位于第二行存储器单元内并且其中第一行存储器单元连续地邻近第二行存储器单元。存储器阵列还包括交替的第一和第二位线，其中第一行存储器单元的每个存储器单元耦合到第一位线中的相应一个，其中第二行存储器单元的每个存储器单元耦合到所述第二位线中的相应一个，并且其中所述第一位线与所述第二位线不同。

8. 发明申请

US20060292767A1 STORAGE DEVICES FORMED ON PARTIALLY ISOLATED SEMICONDUCTOR SUBSTRATE ISLANDS 审中-公开
标题翻译：在部分隔离半导体基板岛上形成的存储器件
公开(公告)号：US20060292767A1
公开(公告)日：2006-12-28
申请号：US11458970
申请日：2006-07-20
申请人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
发明人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
IPC分类号： H01L21/84 , H01L29/76
CPC分类号： H01L21/26506 , H01L21/76235 , H01L21/76264 , H01L21/76281 , H01L21/76289 , H01L21/764 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/0214 , H01L27/10811 , H01L27/10844 , H01L27/10873 , H01L27/11521 , H01L27/1203 , H01L28/91 , H01L29/7846
摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.
摘要翻译：公开了一种制造绝缘体上部分硅片的工艺。在衬底中产生深的注入区域。在横向腔蚀刻期间，深注入区域抵抗蚀刻。侧腔蚀刻用于部分隔离深注入区域上方的有效区域。根据实施例，在各种处理阶段形成深注入区域。还公开了通过该过程实现的主动装置。还公开了一种使用有源器件的系统。

9. 发明申请

US20050279985A1 Three dimensional flash cell 有权
公开(公告)号：US20050279985A1
公开(公告)日：2005-12-22
申请号：US11210523
申请日：2005-08-24
申请人： Roger Lindsay , Lyle Jones
发明人： Roger Lindsay , Lyle Jones
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/00
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.

10. 发明申请

US20100035395A1 METHODS OF FORMING MEMORY CELLS ON PILLARS AND MEMORIES WITH MEMORY CELLS ON PILLARS 有权
标题翻译：在支架上存储细胞形成记忆细胞的方法
公开(公告)号：US20100035395A1
公开(公告)日：2010-02-11
申请号：US12579927
申请日：2009-10-15
申请人： Roger W. Lindsay , Lyle Jones
发明人： Roger W. Lindsay , Lyle Jones
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： Methods of fabricating memory are disclosed. For example, a method includes fabricating rows of memory cells on pillars separated by isolation regions therebetween. Each pillar has a pair of memory cells, each on an opposite side thereof. The method also includes fabricating control gates substantially between the rows of memory cells, each control gate to control half the cells of each of its adjacent rows of memory cells, and fabricating word lines for the array, the word lines extending substantially parallel to the control gates for the cells.
摘要翻译：公开了制造存储器的方法。例如，一种方法包括在由它们之间的隔离区隔开的柱上制造存储单元行。每个支柱具有一对存储单元，每一个在其相对侧上。该方法还包括基本上在存储器单元行之间制造控制栅极，每个控制栅极控制其相邻行存储单元的每一个的单元的一半，并且为阵列制造字线，该字线基本上平行于控制器电池门。

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