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1. 发明申请

US20050280071A1 Three dimensional flash cell 审中-公开
公开(公告)号：US20050280071A1
公开(公告)日：2005-12-22
申请号：US11210524
申请日：2005-08-24
申请人： Roger Lindsay , Lyle Jones
发明人： Roger Lindsay , Lyle Jones
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.

2. 发明申请

US20050279985A1 Three dimensional flash cell 有权
公开(公告)号：US20050279985A1
公开(公告)日：2005-12-22
申请号：US11210523
申请日：2005-08-24
申请人： Roger Lindsay , Lyle Jones
发明人： Roger Lindsay , Lyle Jones
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/00
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.

3. 发明申请

US20060001074A1 Three dimensional flash cell 有权
公开(公告)号：US20060001074A1
公开(公告)日：2006-01-05
申请号：US11210518
申请日：2005-08-24
申请人： Roger Lindsay , Lyle Jones
发明人： Roger Lindsay , Lyle Jones
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.

4. 发明申请

US20050279984A1 Three dimensional flash cell 审中-公开
标题翻译：三维闪电池
公开(公告)号：US20050279984A1
公开(公告)日：2005-12-22
申请号：US11210389
申请日：2005-08-24
申请人： Roger Lindsay , Lyle Jones
发明人： Roger Lindsay , Lyle Jones
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/00
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7881
摘要： A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
摘要翻译：浮动栅极存储单元包括相邻单元之间的隔离区域和单元格列的交错图案。字线与控制栅极结构平行。

5. 发明申请

US20050281092A1 Nand memory arrays 有权
标题翻译： Nand存储器阵列
公开(公告)号：US20050281092A1
公开(公告)日：2005-12-22
申请号：US11209301
申请日：2005-08-23
申请人： Roger Lindsay
发明人： Roger Lindsay
IPC分类号： H01L21/60 , H01L21/8247 , H01L27/115 , G11C7/10
CPC分类号： H01L27/11521 , H01L21/76897 , H01L27/115
摘要： A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate and is connected in series between the source select gate and the drain select gate. A drain contact has a head connected substantially perpendicularly to a stem. The head is aligned with the drain select gate and overlies a dielectric layer formed on the drain select gate. The stem overlies a polysilicon plug formed on the substrate. A bit line contact is in direct electrical contact with the head.
摘要翻译： NAND存储器阵列具有衬底，形成在衬底上的源极选择栅极和形成在衬底上的漏极选择栅极。在衬底上形成一串浮栅存储单元，并串联连接在源选择栅极和漏极选择栅极之间。漏极接触头具有基本垂直于杆的连接头。磁头与漏极选择栅极对准，并覆盖形成在漏极选择栅极上的电介质层。茎覆盖形成在基底上的多晶硅塞。位线接触器与头部直接电接触。

6. 发明申请

US20050279983A1 Source lines for NAND memory devices 有权
标题翻译： NAND存储器件的源极线
公开(公告)号：US20050279983A1
公开(公告)日：2005-12-22
申请号：US11209487
申请日：2005-08-23
申请人： Mark Helm , Roger Lindsay
发明人： Mark Helm , Roger Lindsay
IPC分类号： G11C16/04 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/00
CPC分类号： H01L27/11524 , G11C16/0483 , H01L21/76895 , H01L27/115 , H01L27/11521
摘要： A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
摘要翻译： NAND存储器件具有连接到两个或更多个串联连接的浮栅晶体管的源极线。源极线包括形成在衬底上并耦合到与两个或更多个串联连接的浮栅晶体管的列相关联的源极选择栅极的第一导电层。源极线还包括形成在第一导电层上的第二导电层，其中第二层具有比第一导电层更大的导电性。

7. 发明申请

US20060197138A1 Use of selective epitaxial silicon growth in formation of floating gates 审中-公开
标题翻译：使用选择性外延硅生长形成浮栅
公开(公告)号：US20060197138A1
公开(公告)日：2006-09-07
申请号：US11416830
申请日：2006-05-03
申请人： Roger Lindsay
发明人： Roger Lindsay
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/66545
摘要： Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the capability of the patterning technology, e.g., photolithography.
摘要翻译：利用外延硅生长在浮栅存储器单元的浮动栅极的基极结构上的装置，以增加浮栅的可用耦合面积，同时减小相邻存储单元之间的间隔。外延硅生长有利于相邻电池之间的间隔的减小超过图案化技术的能力，例如光刻。

8. 发明申请

US20060003588A1 Flash memory cells with reduced distances between cell elements 有权
标题翻译：闪存单元与单元元件之间的距离减小
公开(公告)号：US20060003588A1
公开(公告)日：2006-01-05
申请号：US10881042
申请日：2004-06-30
申请人： Roger Lindsay , Frances May , Robert Veltrop
发明人： Roger Lindsay , Frances May , Robert Veltrop
IPC分类号： H01L29/76 , H01L21/311
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28273 , H01L21/31116 , H01L21/31138 , H01L27/11521 , H01L29/66825
摘要： An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.
摘要翻译：在细胞制造过程中涉及的各种层上形成抗反射涂层（ARC）。选择性地蚀刻ARC，使得ARC蚀刻区域的边缘以由ARC的厚度确定的角度向下倾斜。蚀刻工艺可以包括CF 4 O 3化学。倾斜的ARC区域的内边缘减少了原始的照片定义的空间，因为下面的层现在由倾斜的边缘限定。

9. 发明申请

US20050266678A1 Source lines for NAND memory devices 有权
标题翻译： NAND存储器件的源极线
公开(公告)号：US20050266678A1
公开(公告)日：2005-12-01
申请号：US10855844
申请日：2004-05-27
申请人： Mark Helm , Roger Lindsay
发明人： Mark Helm , Roger Lindsay
IPC分类号： G11C16/04 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/00
CPC分类号： H01L27/11524 , G11C16/0483 , H01L21/76895 , H01L27/115 , H01L27/11521
摘要： Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
摘要翻译：提供了方法和装置。 NAND存储器件具有连接到两个或更多个串联连接的浮栅晶体管的源极线。源极线包括形成在衬底上并耦合到与两个或更多个串联连接的浮栅晶体管的列相关联的源极选择栅极的第一导电层。源极线还包括形成在第一导电层上的第二导电层，其中第二层具有比第一导电层更大的导电性。

10. 发明申请

US20060208308A1 Use of selective epitaxial silicon growth in formation of floating gates 审中-公开
公开(公告)号：US20060208308A1
公开(公告)日：2006-09-21
申请号：US11416595
申请日：2006-05-03
申请人： Roger Lindsay
发明人： Roger Lindsay
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/66545
摘要： Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the capability of the patterning technology, e.g., photolithography.

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